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Searched refs:__raw_writew (Results 1 – 25 of 137) sorted by relevance

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/arch/sh/include/mach-se/mach/
Dmrshpc.h12 __raw_writew(0x0674, MRSHPC_CPWCR); /* Card Vcc is 3.3v? */ in mrshpc_setup_windows()
14 __raw_writew(0x0678, MRSHPC_CPWCR); /* Card Vcc is 5V */ in mrshpc_setup_windows()
22 __raw_writew(0x8a84, MRSHPC_MW0CR1); in mrshpc_setup_windows()
25 __raw_writew(0x0b00, MRSHPC_MW0CR2); in mrshpc_setup_windows()
28 __raw_writew(0x0300, MRSHPC_MW0CR2); in mrshpc_setup_windows()
31 __raw_writew(0x8a85, MRSHPC_MW1CR1); in mrshpc_setup_windows()
34 __raw_writew(0x0a00, MRSHPC_MW1CR2); in mrshpc_setup_windows()
37 __raw_writew(0x0200, MRSHPC_MW1CR2); in mrshpc_setup_windows()
40 __raw_writew(0x8a86, MRSHPC_IOWCR1); in mrshpc_setup_windows()
41 __raw_writew(0x0008, MRSHPC_CDCR); /* I/O card mode */ in mrshpc_setup_windows()
[all …]
/arch/sh/boards/mach-se/7780/
Dsetup.c78 __raw_writew( 'S' , PA_LED_DISP + (DISP_SEL0_ADDR << 1) ); in se7780_setup()
79 __raw_writew( 'H' , PA_LED_DISP + (DISP_SEL1_ADDR << 1) ); in se7780_setup()
80 __raw_writew( '-' , PA_LED_DISP + (DISP_SEL2_ADDR << 1) ); in se7780_setup()
81 __raw_writew( 'L' , PA_LED_DISP + (DISP_SEL3_ADDR << 1) ); in se7780_setup()
82 __raw_writew( 'i' , PA_LED_DISP + (DISP_SEL4_ADDR << 1) ); in se7780_setup()
83 __raw_writew( 'n' , PA_LED_DISP + (DISP_SEL5_ADDR << 1) ); in se7780_setup()
84 __raw_writew( 'u' , PA_LED_DISP + (DISP_SEL6_ADDR << 1) ); in se7780_setup()
85 __raw_writew( 'x' , PA_LED_DISP + (DISP_SEL7_ADDR << 1) ); in se7780_setup()
96 __raw_writew(0x0213, FPGA_REQSEL); in se7780_setup()
99 __raw_writew(0x0000, GPIO_PECR); in se7780_setup()
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Dirq.c27 __raw_writew(0, FPGA_INTMSK1); in init_se7780_IRQ()
29 __raw_writew((__raw_readw(FPGA_INTMSK1) | 0x0002), FPGA_INTMSK1); in init_se7780_IRQ()
31 __raw_writew(0, FPGA_INTMSK2); in init_se7780_IRQ()
35 __raw_writew( ((IRQPIN_SM501 << IRQPOS_SM501) | in init_se7780_IRQ()
39 __raw_writew(((IRQPIN_EXTINT4 << IRQPOS_EXTINT4) | in init_se7780_IRQ()
45 __raw_writew((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3); in init_se7780_IRQ()
66 __raw_writew(0x0013, FPGA_PCI_INTSEL1); in init_se7780_IRQ()
67 __raw_writew(0xE402, FPGA_PCI_INTSEL2); in init_se7780_IRQ()
/arch/sh/boards/
Dboard-magicpanelr2.c94 __raw_writew(0x5555, PORT_PACR); /* 01 01 01 01 01 01 01 01 */ in setup_port_multiplexing()
99 __raw_writew(0x5555, PORT_PBCR); /* 01 01 01 01 01 01 01 01 */ in setup_port_multiplexing()
104 __raw_writew(0x5500, PORT_PCCR); /* 01 01 01 01 00 00 00 00 */ in setup_port_multiplexing()
109 __raw_writew(0x5555, PORT_PDCR); /* 01 01 01 01 01 01 01 01 */ in setup_port_multiplexing()
114 __raw_writew(0x3C00, PORT_PECR); /* 00 11 11 00 00 00 00 00 */ in setup_port_multiplexing()
119 __raw_writew(0x0002, PORT_PFCR); /* 00 00 00 00 00 00 00 10 */ in setup_port_multiplexing()
124 __raw_writew(0x03D5, PORT_PGCR); /* 00 00 00 11 11 01 01 01 */ in setup_port_multiplexing()
129 __raw_writew(0x0050, PORT_PHCR); /* 00 00 00 00 01 01 00 00 */ in setup_port_multiplexing()
134 __raw_writew(0x0000, PORT_PJCR); /* 00 00 00 00 00 00 00 00 */ in setup_port_multiplexing()
139 __raw_writew(0x00FF, PORT_PKCR); /* 00 00 00 00 11 11 11 11 */ in setup_port_multiplexing()
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Dboard-polaris.c95 __raw_writew(wcr, WCR2); in polaris_initialise()
100 __raw_writew(bcr_mask, BCR2); in polaris_initialise()
131 __raw_writew(0, BCR_ILCRA); in init_polaris_irq()
132 __raw_writew(0, BCR_ILCRB); in init_polaris_irq()
133 __raw_writew(0, BCR_ILCRC); in init_polaris_irq()
134 __raw_writew(0, BCR_ILCRD); in init_polaris_irq()
135 __raw_writew(0, BCR_ILCRE); in init_polaris_irq()
136 __raw_writew(0, BCR_ILCRF); in init_polaris_irq()
137 __raw_writew(0, BCR_ILCRG); in init_polaris_irq()
/arch/sh/boards/mach-sh7763rdp/
Dsetup.c173 __raw_writew((__raw_readw(PORT_PSEL2) & 0xFFC3), PORT_PSEL2); in sh7763rdp_setup()
175 __raw_writew(__raw_readw(PORT_PICR) & 0xFC0F, PORT_PICR); in sh7763rdp_setup()
178 __raw_writew(0x00, USB_USBHSC); in sh7763rdp_setup()
182 __raw_writew(__raw_readw(PORT_PJCR) & 0x0003, PORT_PJCR); in sh7763rdp_setup()
184 __raw_writew(__raw_readw(PORT_PICR) & 0xF3FF, PORT_PICR); in sh7763rdp_setup()
185 __raw_writew(0, PORT_PKCR); in sh7763rdp_setup()
186 __raw_writew(0, PORT_PLCR); in sh7763rdp_setup()
188 __raw_writew((__raw_readw(PORT_PSEL2) & 0x00C0), PORT_PSEL2); in sh7763rdp_setup()
190 __raw_writew((__raw_readw(PORT_PSEL3) & 0x0700), PORT_PSEL3); in sh7763rdp_setup()
194 __raw_writew((__raw_readw(PORT_PSEL1) & 0xFFF0) | 0x0004, PORT_PSEL1); in sh7763rdp_setup()
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/arch/sh/boards/mach-se/7722/
Dsetup.c156 __raw_writew(0x010D, FPGA_OUT); /* FPGA */ in se7722_setup()
158 __raw_writew(0x0000, PORT_PECR); /* PORT E 1 = IRQ5 ,E 0 = BS */ in se7722_setup()
159 __raw_writew(0x1000, PORT_PJCR); /* PORT J 1 = IRQ1,J 0 =IRQ0 */ in se7722_setup()
162 __raw_writew(0x0020, PORT_PSELD); in se7722_setup()
165 __raw_writew(0x0003, PORT_PSELB); in se7722_setup()
166 __raw_writew(0xe000, PORT_PSELC); in se7722_setup()
167 __raw_writew(0x0000, PORT_PKCR); in se7722_setup()
170 __raw_writew(0x4020, PORT_PHCR); in se7722_setup()
171 __raw_writew(0x0000, PORT_PLCR); in se7722_setup()
172 __raw_writew(0x0000, PORT_PMCR); in se7722_setup()
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Dirq.c24 __raw_writew(__raw_readw(IRQ01_MASK) | 1 << bit, IRQ01_MASK); in disable_se7722_irq()
30 __raw_writew(__raw_readw(IRQ01_MASK) & ~(1 << bit), IRQ01_MASK); in enable_se7722_irq()
61 __raw_writew(0, IRQ01_MASK); /* disable all irqs */ in init_se7722_IRQ()
62 __raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */ in init_se7722_IRQ()
/arch/sh/boards/mach-se/770x/
Dirq.c99 __raw_writew(0, BCR_ILCRA); in init_se_IRQ()
100 __raw_writew(0, BCR_ILCRB); in init_se_IRQ()
101 __raw_writew(0, BCR_ILCRC); in init_se_IRQ()
102 __raw_writew(0, BCR_ILCRD); in init_se_IRQ()
103 __raw_writew(0, BCR_ILCRE); in init_se_IRQ()
104 __raw_writew(0, BCR_ILCRF); in init_se_IRQ()
105 __raw_writew(0, BCR_ILCRG); in init_se_IRQ()
/arch/sh/boards/mach-se/7206/
Dirq.c38 __raw_writew(val, INTC_IPR01); in disable_se7206_irq()
55 __raw_writew(msk0, INTMSK0); in disable_se7206_irq()
56 __raw_writew(msk1, INTMSK1); in disable_se7206_irq()
69 __raw_writew(val, INTC_IPR01); in enable_se7206_irq()
87 __raw_writew(msk0, INTMSK0); in enable_se7206_irq()
88 __raw_writew(msk1, INTMSK1); in enable_se7206_irq()
114 __raw_writew(sts0, INTSTS0); in eoi_se7206_irq()
115 __raw_writew(sts1, INTSTS1); in eoi_se7206_irq()
142 __raw_writew(__raw_readw(INTC_ICR1) | 0x000b, INTC_ICR1); /* ICR1 */ in init_se7206_IRQ()
145 __raw_writew(0x0000,INTSTS0); /* Clear INTSTS0 */ in init_se7206_IRQ()
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/arch/sh/boot/romimage/
Dmmcif-sh7724.c39 __raw_writew(0x0000, PTWCR); in mmcif_loader()
42 __raw_writew(__raw_readw(PTXCR) & ~0x000f, PTXCR); in mmcif_loader()
45 __raw_writew(__raw_readw(PSELA) & ~0x2000, PSELA); in mmcif_loader()
48 __raw_writew(__raw_readw(PSELE) & ~0x3000, PSELE); in mmcif_loader()
51 __raw_writew(__raw_readw(HIZCRC) & ~0x0620, HIZCRC); in mmcif_loader()
54 __raw_writew(__raw_readw(DRVCRA) | 0x3000, DRVCRA); in mmcif_loader()
/arch/sh/boards/mach-highlander/
Dirq-r7785rp.c74 __raw_writew(0x0000, PA_IRLSSR1); /* FPGA IRLSSR1(CF_CD clear) */ in highlander_plat_irq_setup()
77 __raw_writew(0x0000, PA_IRLPRA); /* FPGA IRLA */ in highlander_plat_irq_setup()
78 __raw_writew(0xe598, PA_IRLPRB); /* FPGA IRLB */ in highlander_plat_irq_setup()
79 __raw_writew(0x7060, PA_IRLPRC); /* FPGA IRLC */ in highlander_plat_irq_setup()
80 __raw_writew(0x0000, PA_IRLPRD); /* FPGA IRLD */ in highlander_plat_irq_setup()
81 __raw_writew(0x4321, PA_IRLPRE); /* FPGA IRLE */ in highlander_plat_irq_setup()
82 __raw_writew(0xdcba, PA_IRLPRF); /* FPGA IRLF */ in highlander_plat_irq_setup()
/arch/m68k/platform/coldfire/
Dpit.c51 __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR)); in init_cf_pit_timer()
52 __raw_writew(PIT_CYCLES_PER_JIFFY, TA(MCFPIT_PMR)); in init_cf_pit_timer()
53 __raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE | \ in init_cf_pit_timer()
61 __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR)); in init_cf_pit_timer()
66 __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR)); in init_cf_pit_timer()
67 __raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE | \ in init_cf_pit_timer()
86 __raw_writew(delta, TA(MCFPIT_PMR)); in cf_pit_next_event()
110 __raw_writew(pcsr | MCFPIT_PCSR_PIF, TA(MCFPIT_PCSR)); in pit_tick()
Dtimers.c44 #define __raw_writetrr __raw_writew
120 __raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR)); in hw_timer_init()
129 __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 | in hw_timer_init()
184 __raw_writew(MCFTIMER_TMR_DISABLE, PA(MCFTIMER_TMR)); in coldfire_profile_init()
187 __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 | in coldfire_profile_init()
/arch/sh/boards/mach-se/7724/
Dirq.c76 __raw_writew(__raw_readw(set.mraddr) | 0x0001 << bit, set.mraddr); in disable_se7724_irq()
84 __raw_writew(__raw_readw(set.mraddr) & ~(0x0001 << bit), set.mraddr); in enable_se7724_irq()
116 __raw_writew(0xffff, IRQ0_MR); /* mask all */ in init_se7724_IRQ()
117 __raw_writew(0xffff, IRQ1_MR); /* mask all */ in init_se7724_IRQ()
118 __raw_writew(0xffff, IRQ2_MR); /* mask all */ in init_se7724_IRQ()
119 __raw_writew(0x0000, IRQ0_SR); /* clear irq */ in init_se7724_IRQ()
120 __raw_writew(0x0000, IRQ1_SR); /* clear irq */ in init_se7724_IRQ()
121 __raw_writew(0x0000, IRQ2_SR); /* clear irq */ in init_se7724_IRQ()
122 __raw_writew(0x002a, IRQ_MODE); /* set irq type */ in init_se7724_IRQ()
/arch/sh/kernel/cpu/sh3/
Dserial-sh7720.c16 __raw_writew((data & 0xfc03), PORT_PTCR); in sh7720_sci_init_pins()
20 __raw_writew((data & 0xfc03), PORT_PVCR); in sh7720_sci_init_pins()
26 __raw_writew((data & 0xffc3), PORT_PTCR); in sh7720_sci_init_pins()
30 __raw_writew((data & 0xffc3), PORT_PVCR); in sh7720_sci_init_pins()
Dserial-sh7710.c12 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR); in sh7710_sci_init_pins()
13 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR); in sh7710_sci_init_pins()
15 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR); in sh7710_sci_init_pins()
/arch/mips/alchemy/devboards/
Dbcsr.c64 __raw_writew(val, bcsr_regs[reg].raddr); in bcsr_write()
79 __raw_writew(r, bcsr_regs[reg].raddr); in bcsr_mod()
103 __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR); in bcsr_irq_mask()
110 __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR); in bcsr_irq_maskack()
111 __raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT); /* ack */ in bcsr_irq_maskack()
118 __raw_writew(v, bcsr_virt + BCSR_REG_MASKSET); in bcsr_irq_unmask()
134 __raw_writew(0xffff, bcsr_virt + BCSR_REG_MASKCLR); in bcsr_init_irq()
135 __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSET); in bcsr_init_irq()
136 __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSTAT); in bcsr_init_irq()
/arch/sh/boards/mach-hp6xx/
Dpm.c59 __raw_writew(frqcr, FRQCR); in pm_enter()
67 __raw_writew(mcr & ~MCR_RFSH, MCR); in pm_enter()
77 __raw_writew(0, RTCNT); in pm_enter()
78 __raw_writew(mcr | MCR_RFSH | MCR_RMODE, MCR); in pm_enter()
89 __raw_writew(frqcr, FRQCR); in pm_enter()
92 __raw_writew(frqcr, FRQCR); in pm_enter()
/arch/sh/boards/mach-se/7721/
Dsetup.c83 __raw_writew(0x0000, 0xA405010C); /* PGCR */ in se7721_setup()
84 __raw_writew(0x0000, 0xA405010E); /* PHCR */ in se7721_setup()
85 __raw_writew(0x00AA, 0xA4050118); /* PPCR */ in se7721_setup()
86 __raw_writew(0x0000, 0xA4050124); /* PSELA */ in se7721_setup()
/arch/arm/plat-mxc/
D3ds_debugboard.c125 __raw_writew(reg, brd_io + INTR_MASK_REG); in expio_mask_irq()
132 __raw_writew(1 << expio, brd_io + INTR_RESET_REG); in expio_ack_irq()
133 __raw_writew(0, brd_io + INTR_RESET_REG); in expio_ack_irq()
144 __raw_writew(reg, brd_io + INTR_MASK_REG); in expio_unmask_irq()
185 __raw_writew(0, brd_io + INTR_MASK_REG); in mxc_expio_init()
186 __raw_writew(0xFFFF, brd_io + INTR_RESET_REG); in mxc_expio_init()
187 __raw_writew(0, brd_io + INTR_RESET_REG); in mxc_expio_init()
188 __raw_writew(0x1F, brd_io + INTR_MASK_REG); in mxc_expio_init()
/arch/sh/boards/mach-se/7343/
Dirq.c24 __raw_writew(__raw_readw(PA_CPLD_IMSK) | 1 << bit, PA_CPLD_IMSK); in disable_se7343_irq()
30 __raw_writew(__raw_readw(PA_CPLD_IMSK) & ~(1 << bit), PA_CPLD_IMSK); in enable_se7343_irq()
61 __raw_writew(0, PA_CPLD_IMSK); /* disable all irqs */ in init_7343se_IRQ()
62 __raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */ in init_7343se_IRQ()
/arch/sparc/include/asm/
Dide.h74 __raw_writew(*ps++, port); in __ide_outsw()
82 __raw_writew((w >> 16), port); in __ide_outsw()
83 __raw_writew(w, port); in __ide_outsw()
88 __raw_writew(*ps, port); in __ide_outsw()
/arch/m68k/platform/5272/
Dconfig.c53 __raw_writew(0, MCF_MBAR + MCFSIM_WIRR); in m5272_cpu_reset()
54 __raw_writew(1, MCF_MBAR + MCFSIM_WRRR); in m5272_cpu_reset()
55 __raw_writew(0, MCF_MBAR + MCFSIM_WCR); in m5272_cpu_reset()
/arch/sh/cchips/hd6446x/
Dhd64461.c28 __raw_writew(nimr, HD64461_NIMR); in hd64461_mask_irq()
39 __raw_writew(nimr, HD64461_NIMR); in hd64461_unmask_irq()
88 __raw_writew(0x2240, INTC_ICR1); in setup_hd64461()
90 __raw_writew(0xffff, HD64461_NIMR); in setup_hd64461()

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