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Searched refs:__region_CS2 (Results 1 – 7 of 7) sorted by relevance

/arch/frv/include/asm/
Dmb-regs.h47 #define __region_CS2 0xe0000000 /* SLBUS/PCI I/O space */ macro
69 #define __region_PCI_IO (__region_CS2 + 0x04000000UL)
70 #define __region_PCI_MEM (__region_CS2 + 0x08000000UL)
85 #define __get_CLKSW() ({ *(volatile unsigned long *)(__region_CS2 + 0x0130000cUL) & 0xffUL; })
92 #define __addr_LEDS() (__region_CS2 + 0x01200004UL)
103 #define __addr_LCD() (__region_CS2 + 0x01200008UL)
144 #define __region_CS2 0x20000000 /* FPGA registers */ macro
174 #define __addr_LEDS() (__region_CS2 + 0x00000023UL)
177 #define __addr_FPGATR() (__region_CS2 + 0x00000030UL)
194 #define __addr_FPGA_SWR ((volatile void __iomem *)(__region_CS2 + 0x28UL))
Dmb86943a.h39 #define __reg_MB86943_pci_arbiter *(volatile uint32_t *) (__region_CS2 + 0x01300014)
/arch/frv/mb93090-mb00/
Dpci-vdk.c362 __reg_MB86943_ecs_base(1) = ((__region_CS2 + 0x01000000) >> 9) | 0x08000000; in pcibios_init()
363 __reg_MB86943_ecs_base(2) = ((__region_CS2 + 0x00000000) >> 9) | 0x08000000; in pcibios_init()
368 __reg_MB86943_sl_pci_io_base = (__region_CS2 + 0x04000000) >> 9; in pcibios_init()
369 __reg_MB86943_sl_pci_mem_base = (__region_CS2 + 0x08000000) >> 9; in pcibios_init()
370 __reg_MB86943_pci_sl_io_base = __region_CS2 + 0x04000000; in pcibios_init()
371 __reg_MB86943_pci_sl_mem_base = __region_CS2 + 0x08000000; in pcibios_init()
/arch/frv/kernel/
Dhead-uc-fr401.S109 sethi.p %hi(__region_CS2),gr4
110 setlo %lo(__region_CS2),gr4
167 sethi.p %hi(LED_ADDR - 0x20000000 +__region_CS2),gr30
168 setlo %lo(LED_ADDR - 0x20000000 +__region_CS2),gr30
273 sethi.p %hi(__region_CS2),gr4
274 setlo %lo(__region_CS2),gr4
Dirq-mb93093.c27 #define __reg16(ADDR) (*(volatile unsigned short *)(__region_CS2 + (ADDR)))
Dhead-mmu-fr451.S102 sethi.p %hi(__region_CS2),gr4
103 setlo %lo(__region_CS2),gr4
161 sethi.p %hi(__region_CS2 + 0x01200004),gr30
162 setlo %lo(__region_CS2 + 0x01200004),gr30
Dhead-uc-fr555.S95 sethi.p %hi(__region_CS2),gr4
96 setlo %lo(__region_CS2),gr4
154 sethi.p %hi(LED_ADDR - 0x20000000 +__region_CS2),gr30
155 setlo %lo(LED_ADDR - 0x20000000 +__region_CS2),gr30