| /arch/sh/kernel/cpu/sh4a/ |
| D | clock-sh7366.c | 120 #define DIV4(_reg, _bit, _mask, _flags) \ argument
121 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
140 #define MSTP(_parent, _reg, _bit, _flags) \ argument
141 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
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| D | clock-sh7757.c | 65 #define DIV4(_bit, _mask, _flags) \ argument
66 SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags)
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| D | clock-shx3.c | 64 #define DIV4(_bit, _mask, _flags) \ argument
65 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
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| D | clock-sh7343.c | 117 #define DIV4(_reg, _bit, _mask, _flags) \ argument
118 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
137 #define MSTP(_parent, _reg, _bit, _flags) \ argument
138 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
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| D | clock-sh7785.c | 69 #define DIV4(_bit, _mask, _flags) \ argument
70 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
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| D | clock-sh7786.c | 70 #define DIV4(_bit, _mask, _flags) \ argument
71 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
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| D | clock-sh7722.c | 120 #define DIV4(_reg, _bit, _mask, _flags) \ argument
121 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
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| D | clock-sh7723.c | 123 #define DIV4(_reg, _bit, _mask, _flags) \ argument
124 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
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| D | clock-sh7724.c | 162 #define DIV4(_reg, _bit, _mask, _flags) \ argument
163 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
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| /arch/arm/mach-shmobile/ |
| D | clock-sh7377.c | 189 #define DIV4(_reg, _bit, _mask, _flags) \ argument
190 SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
239 #define MSTP(_parent, _reg, _bit, _flags) \ argument
240 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
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| D | clock-sh7367.c | 179 #define DIV4(_reg, _bit, _mask, _flags) \ argument
180 SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
228 #define MSTP(_parent, _reg, _bit, _flags) \ argument
229 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
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| D | clock-sh73a0.c | 263 #define DIV4(_reg, _bit, _mask, _flags) \ argument
264 SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags)
486 #define MSTP(_parent, _reg, _bit, _flags) \ argument
487 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
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| D | clock-sh7372.c | 349 #define DIV4(_reg, _bit, _mask, _flags) \ argument
350 SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
519 #define MSTP(_parent, _reg, _bit, _flags) \ argument
520 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
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