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Searched refs:_parent (Results 1 – 9 of 9) sorted by relevance

/arch/sh/kernel/cpu/sh4a/
Dclock-sh7366.c140 #define MSTP(_parent, _reg, _bit, _flags) \ argument
141 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
Dclock-sh7343.c137 #define MSTP(_parent, _reg, _bit, _flags) \ argument
138 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
/arch/arm/mach-shmobile/
Dclock-sh7377.c239 #define MSTP(_parent, _reg, _bit, _flags) \ argument
240 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
Dclock-sh7367.c228 #define MSTP(_parent, _reg, _bit, _flags) \ argument
229 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
Dclock-sh73a0.c486 #define MSTP(_parent, _reg, _bit, _flags) \ argument
487 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
Dclock-sh7372.c519 #define MSTP(_parent, _reg, _bit, _flags) \ argument
520 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
/arch/arm/mach-davinci/
Dtnetv107x.c165 #define __lpsc_clk(cname, _parent, mod, flg) \ argument
168 .parent = &_parent, \
/arch/arm/mach-tegra/
Dtegra2_clocks.c2130 #define SHARED_CLK(_name, _dev, _con, _parent) \ argument
2138 .parent = _parent, \
Dtegra30_clocks.c2858 #define SHARED_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\ argument
2866 .parent = _parent, \