Home
last modified time | relevance | path

Searched refs:ar (Results 1 – 25 of 64) sorted by relevance

123

/arch/xtensa/include/asm/
Dcacheasm.h34 .macro __loop_cache_all ar at insn size line_width
36 movi \ar, 0
38 __loopi \ar, \at, \size, (4 << (\line_width))
39 \insn \ar, 0 << (\line_width)
40 \insn \ar, 1 << (\line_width)
41 \insn \ar, 2 << (\line_width)
42 \insn \ar, 3 << (\line_width)
43 __endla \ar, \at, 4 << (\line_width)
48 .macro __loop_cache_range ar as at insn line_width
50 extui \at, \ar, 0, \line_width
[all …]
Dasmmacro.h48 .macro __loopi ar, at, size, incr
54 addi \at, \ar, \size
64 .macro __loops ar, as, at, incr_log2, mask_log2, cond, ncond
90 add \at, \ar, \at
92 add \at, \ar, \as
103 .macro __loopt ar, as, at, incr_log2
106 sub \at, \as, \ar
136 .macro __endl ar, as
138 bltu \ar, \as, 98b
147 .macro __endla ar, as, incr
[all …]
/arch/ia64/lib/
Dxor.S21 .save ar.pfs, r31
22 alloc r31 = ar.pfs, 3, 0, 13, 16
23 .save ar.lc, r30
24 mov r30 = ar.lc
30 mov ar.ec = 6 + 2
37 mov ar.lc = in0
50 mov ar.lc = r30
58 .save ar.pfs, r31
59 alloc r31 = ar.pfs, 4, 0, 20, 24
60 .save ar.lc, r30
[all …]
Dflush.S27 alloc r2=ar.pfs,2,0,0,0
41 .save ar.lc,r3
42 mov r3=ar.lc // save ar.lc
46 mov ar.lc=r8
60 mov ar.lc=r3 // restore ar.lc
79 alloc r2=ar.pfs,2,0,0,0
95 .save ar.lc,r3
96 mov r3=ar.lc // save ar.lc
100 mov ar.lc=r8
115 mov ar.lc=r3 // restore ar.lc
Dstrnlen_user.S19 alloc r2=ar.pfs,2,0,0,0
20 .save ar.lc, r16
21 mov r16=ar.lc // preserve ar.lc
27 mov ar.lc=r3
43 mov ar.lc=r16 // restore ar.lc
Dcopy_user.S75 .save ar.pfs, saved_pfs
76 alloc saved_pfs=ar.pfs,3,((2*PIPE_DEPTH+7)&~7),0,((2*PIPE_DEPTH+7)&~7)
86 .save ar.lc, saved_lc
87 mov saved_lc=ar.lc // preserve ar.lc (slow)
98 mov ar.ec=PIPE_DEPTH
102 mov ar.lc=len2 // initialize lc for small count
117 mov ar.lc=saved_lc
119 mov ar.pfs=saved_pfs // restore ar.ec
190 mov ar.ec=PIPE_DEPTH
192 mov ar.lc=cnt
[all …]
Dmemcpy.S48 .save ar.pfs, saved_pfs
49 alloc saved_pfs=ar.pfs,3,Nrot,0,Nrot
50 .save ar.lc, saved_lc
51 mov saved_lc=ar.lc
73 mov ar.ec=N
77 mov ar.lc=cnt
106 mov ar.lc=saved_lc
108 mov ar.pfs=saved_pfs
120 mov ar.ec=MEM_LAT
123 mov ar.lc=cnt
[all …]
Dcopy_page.S39 .save ar.pfs, saved_pfs
40 alloc saved_pfs=ar.pfs,3,Nrot-3,0,Nrot
46 .save ar.lc, saved_lc
47 mov saved_lc=ar.lc
48 mov ar.ec=PIPE_DEPTH
63 mov ar.lc=lcount
95 mov ar.pfs=saved_pfs
96 mov ar.lc=saved_lc
Dclear_user.S56 .save ar.pfs, saved_pfs
57 alloc saved_pfs=ar.pfs,2,0,0,0
59 .save ar.lc, saved_lc
60 mov saved_lc=ar.lc // preserve ar.lc (slow)
68 mov ar.lc=tmp // initialize lc for small count
89 mov ar.lc=saved_lc
125 mov ar.lc=tmp
153 mov ar.lc=saved_lc
207 mov ar.lc=saved_lc
Dclear_page.S36 .save ar.lc, saved_lc
37 mov saved_lc = ar.lc
40 mov ar.lc = (PREFETCH_LINES - 1)
50 mov ar.lc = r16 // one L3 line per iteration
74 mov ar.lc = saved_lc // restore lc
/arch/ia64/kernel/
Drelocate_kernel.S23 alloc r31=ar.pfs,4,0,0,0
41 mov ar.rsc=0 // put RSE in enforced lazy mode
46 mov r18=ar.rnat
47 mov ar.bspstore=r8
54 mov ar.rnat=r18
83 mov ar.lc=r20
156 mov ar.lc=r14;;
191 alloc loc0=ar.pfs,1,2,0,0
193 mov ar.rsc=0 // put RSE in enforced lazy mode
205 mov r4=ar.rnat
[all …]
Dpal.S32 alloc r3=ar.pfs,1,0,0,0
57 alloc loc1 = ar.pfs,4,5,0,0
67 mov loc4=ar.rsc // save RSE configuration
69 mov ar.rsc=0 // put RSE in enforced lazy, LE mode
83 mov ar.rsc = loc4 // restore RSE configuration
84 mov ar.pfs = loc1
100 alloc loc1 = ar.pfs,4,4,4,0
119 mov ar.pfs = loc1
147 alloc loc1 = ar.pfs,4,7,0,0
164 mov loc4=ar.rsc // save RSE configuration
[all …]
Dgate.S104 .savesp ar.unat, UNAT_OFF+SIGCONTEXT_OFF; \
105 .savesp ar.fpsr, FPSR_OFF+SIGCONTEXT_OFF; \
108 .savesp ar.pfs, CFM_OFF+SIGCONTEXT_OFF; \
128 mov.m r9=ar.bsp // fetch ar.bsp
129 .spillsp.p p1, ar.rnat, RNAT_OFF+SIGCONTEXT_OFF
132 alloc r8=ar.pfs,0,0,3,0
143 .spillsp ar.bsp, BSP_OFF+SIGCONTEXT_OFF
167 mov r14=ar.bsp
197 mov ar.rsc=0 // put RSE into enforced lazy mode
199 .save ar.rnat, r19
[all …]
Dminstate.h10 (pUStk) mov.m r20=ar.itc;
49 mov r27=ar.rsc; /* M */ \
51 mov r25=ar.unat; /* M */ \
53 mov r26=ar.pfs; /* I */ \
55 mov r21=ar.fpsr; /* M */ \
69 (pUStk) mov ar.rsc=0; /* set enforced lazy mode, pl 0, little-endian, loadrs=0 */ \
71 (pUStk) mov.m r24=ar.rnat; \
77 (pUStk) mov r23=ar.bspstore; /* save ar.bspstore */ \
79 (pUStk) mov ar.bspstore=r22; /* switch to kernel RBS */ \
82 (pUStk) mov r18=ar.bsp; \
[all …]
Defi_stub.S47 alloc loc1=ar.pfs,8,7,7,0
53 mov loc4=ar.rsc // save RSE configuration
54 mov ar.rsc=0 // put RSE in enforced lazy, LE mode
76 .ret1: mov ar.rsc=0 // put RSE in enforced lazy, LE mode
81 .ret2: mov ar.rsc=loc4 // restore RSE configuration
82 mov ar.pfs=loc1
Desi_stub.S49 alloc loc1=ar.pfs,2,7,8,0
70 mov loc4=ar.rsc // save RSE configuration
71 mov ar.rsc=0 // put RSE in enforced lazy, LE mode
86 .ret1: mov ar.rsc=0 // put RSE in enforced lazy, LE mode
91 .ret2: mov ar.rsc=loc4 // restore RSE configuration
92 mov ar.pfs=loc1
Dentry.h31 .spillsp ar.pfs, PT(CR_IFS)+16+(off); \
32 .spillsp ar.unat, PT(AR_UNAT)+16+(off); \
33 .spillsp ar.fpsr, PT(AR_FPSR)+16+(off); \
42 .savesp ar.unat,SW(CALLER_UNAT)+16+(off); \
43 .savesp ar.fpsr,SW(AR_FPSR)+16+(off); \
59 .spillsp ar.pfs,SW(AR_PFS)+16+(off); .spillsp ar.lc,SW(AR_LC)+16+(off); \
61 .spillsp ar.rnat,SW(AR_RNAT)+16+(off); \
62 .spillsp ar.bspstore,SW(AR_BSPSTORE)+16+(off); \
Dmca_drv_asm.S20 alloc r16=ar.pfs,0,2,3,0 // make a new frame
21 mov ar.rsc=0
28 mov ar.bspstore=r22
50 mov ar.pfs=loc0
Djprobes.S73 mov r16=ar.rsc
75 mov ar.rsc=r0
79 mov ar.rsc=r16
/arch/ia64/include/asm/
Dmca_asm.h87 mov ar.rsc = 0 ; \
90 mov temp2 = ar.bspstore; \
94 mov temp1 = ar.rnat; \
96 mov ar.bspstore = temp2; \
98 mov ar.rnat = temp1; \
170 mov ar.rsc = 0; \
173 mov r13 = ar.k6; \
174 mov temp2 = ar.bspstore; \
178 mov temp1 = ar.rnat; \
180 mov ar.bspstore = temp2; \
[all …]
/arch/ia64/include/asm/xen/
Dminstate.h38 mov r27=ar.rsc; /* M */ \
40 mov r25=ar.unat; /* M */ \
43 mov r21=ar.fpsr; /* M */ \
44 mov r26=ar.pfs; /* I */ \
57 (pUStk) mov ar.rsc=0; /* set enforced lazy mode, pl 0, little-endian, loadrs=0 */ \
59 (pUStk) mov.m r24=ar.rnat; \
65 (pUStk) mov r23=ar.bspstore; /* save ar.bspstore */ \
67 (pUStk) mov ar.bspstore=r22; /* switch to kernel RBS */ \
70 (pUStk) mov r18=ar.bsp; \
71 (pUStk) mov ar.rsc=0x3; /* set eager mode, pl 0, little-endian, loadrs=0 */ \
[all …]
/arch/ia64/kvm/
Dkvm_minstate.h32 mov ar.rsc = 0;/* set enforced lazy mode, pl 0, little-endian, loadrs=0 */\
34 mov.m r28 = ar.rnat; \
39 mov r23 = ar.bspstore; /* save ar.bspstore */ \
41 mov ar.bspstore = r22; /* switch to kernel RBS */\
43 mov r18 = ar.bsp; \
44 mov ar.rsc = 0x3; /* set eager mode, pl 0, little-endian, loadrs=0 */
102 mov r27 = ar.rsc; /* M */ \
104 mov r25 = ar.unat; /* M */ \
106 mov r26 = ar.pfs; /* I */ \
139 mov r10 = ar.fpsr; /* M */ \
[all …]
Dasm-offsets.c210 DEFINE(VMM_CTX_KR0_OFFSET, offsetof(union context, ar[0])); in foo()
211 DEFINE(VMM_CTX_KR1_OFFSET, offsetof(union context, ar[1])); in foo()
216 DEFINE(VMM_CTX_RSC_OFFSET, offsetof(union context, ar[16])); in foo()
217 DEFINE(VMM_CTX_BSPSTORE_OFFSET, offsetof(union context, ar[18])); in foo()
218 DEFINE(VMM_CTX_RNAT_OFFSET, offsetof(union context, ar[19])); in foo()
219 DEFINE(VMM_CTX_FCR_OFFSET, offsetof(union context, ar[21])); in foo()
220 DEFINE(VMM_CTX_EFLAG_OFFSET, offsetof(union context, ar[24])); in foo()
221 DEFINE(VMM_CTX_CFLG_OFFSET, offsetof(union context, ar[27])); in foo()
222 DEFINE(VMM_CTX_FSR_OFFSET, offsetof(union context, ar[28])); in foo()
223 DEFINE(VMM_CTX_FIR_OFFSET, offsetof(union context, ar[29])); in foo()
[all …]
Dtrampoline.S117 mov r16 = ar.k0; \
118 mov r17 = ar.k1; \
123 mov r16 = ar.k2; \
124 mov r17 = ar.k3; \
129 mov r16 = ar.k4; \
130 mov r17 = ar.k5; \
135 mov r16 = ar.k6; \
136 mov r17 = ar.k7; \
154 mov ar.k0=r16; \
155 mov ar.k1=r17; \
[all …]
Dvmm_ivt.S90 alloc r14=ar.pfs,0,0,1,0
242 alloc r14=ar.pfs,0,0,4,0 //(must be first in insn group!)
276 mov r27=ar.rsc /* M */
278 mov r25=ar.unat /* M */
279 mov r26=ar.pfs /* I */
311 mov r8=ar.fpsr /* M */
312 mov r9=ar.csd
313 mov r10=ar.ssd
346 mov r8=ar.ccv
353 alloc r14=ar.pfs,0,0,1,0 // must be first in an insn group
[all …]

123