Home
last modified time | relevance | path

Searched refs:bank (Results 1 – 25 of 219) sorted by relevance

123456789

/arch/powerpc/sysdev/
Daxonram.c75 struct axon_ram_bank *bank = device->dev.platform_data; in axon_ram_sysfs_ecc() local
77 BUG_ON(!bank); in axon_ram_sysfs_ecc()
79 return sprintf(buf, "%ld\n", bank->ecc_counter); in axon_ram_sysfs_ecc()
93 struct axon_ram_bank *bank = device->dev.platform_data; in axon_ram_irq_handler() local
95 BUG_ON(!bank); in axon_ram_irq_handler()
98 bank->ecc_counter++; in axon_ram_irq_handler()
109 struct axon_ram_bank *bank = bio->bi_bdev->bd_disk->private_data; in axon_ram_make_request() local
116 phys_mem = bank->io_addr + (bio->bi_sector << AXON_RAM_SECTOR_SHIFT); in axon_ram_make_request()
117 phys_end = bank->io_addr + bank->size; in axon_ram_make_request()
145 struct axon_ram_bank *bank = device->bd_disk->private_data; in axon_ram_direct_access() local
[all …]
/arch/unicore32/include/asm/
Dmemblock.h29 struct membank bank[NR_BANKS]; member
37 #define bank_pfn_start(bank) __phys_to_pfn((bank)->start) argument
38 #define bank_pfn_end(bank) __phys_to_pfn((bank)->start + (bank)->size) argument
39 #define bank_pfn_size(bank) ((bank)->size >> PAGE_SHIFT) argument
40 #define bank_phys_start(bank) ((bank)->start) argument
41 #define bank_phys_end(bank) ((bank)->start + (bank)->size) argument
42 #define bank_phys_size(bank) ((bank)->size) argument
/arch/arm/plat-s3c24xx/
Ds3c2412-iotiming.c47 unsigned int bank; in s3c2412_print_timing() local
49 for (bank = 0; bank < MAX_BANKS; bank++) { in s3c2412_print_timing()
50 bt = iot->bank[bank].io_2412; in s3c2412_print_timing()
55 "wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n", pfx, bank, in s3c2412_print_timing()
148 int bank; in s3c2412_iotiming_calc() local
151 for (bank = 0; bank < MAX_BANKS; bank++) { in s3c2412_iotiming_calc()
152 bt = iot->bank[bank].io_2412; in s3c2412_iotiming_calc()
159 __func__, bank); in s3c2412_iotiming_calc()
182 int bank; in s3c2412_iotiming_set() local
186 for (bank = 0; bank < MAX_BANKS; bank++) { in s3c2412_iotiming_set()
[all …]
Ds3c2410-iotiming.c39 int bank; in s3c2410_print_timing() local
41 for (bank = 0; bank < MAX_BANKS; bank++) { in s3c2410_print_timing()
42 bt = timings->bank[bank].io_2410; in s3c2410_print_timing()
47 "Tcoh=%d.%d, Tcah=%d.%d\n", pfx, bank, in s3c2410_print_timing()
60 static inline void __iomem *bank_reg(unsigned int bank) in bank_reg() argument
62 return S3C2410_BANKCON0 + (bank << 2); in bank_reg()
366 int bank; in s3c2410_iotiming_calc() local
369 for (bank = 0; bank < MAX_BANKS; bank++) { in s3c2410_iotiming_calc()
370 bankcon = __raw_readl(bank_reg(bank)); in s3c2410_iotiming_calc()
371 bt = iot->bank[bank].io_2410; in s3c2410_iotiming_calc()
[all …]
/arch/arm/plat-s5p/
Dirq-gpioint.c82 struct s5p_gpioint_bank *bank = irq_get_handler_data(irq); in s5p_gpioint_handler() local
89 for (group = 0; group < bank->nr_groups; group++) { in s5p_gpioint_handler()
90 struct samsung_gpio_chip *chip = bank->chips[group]; in s5p_gpioint_handler()
117 struct s5p_gpioint_bank *b, *bank = NULL; in s5p_gpioint_add() local
126 bank = b; in s5p_gpioint_add()
130 if (!bank) in s5p_gpioint_add()
133 if (!bank->handler) { in s5p_gpioint_add()
134 bank->chips = kzalloc(sizeof(struct samsung_gpio_chip *) * in s5p_gpioint_add()
135 bank->nr_groups, GFP_KERNEL); in s5p_gpioint_add()
136 if (!bank->chips) in s5p_gpioint_add()
[all …]
/arch/x86/kernel/cpu/mcheck/
Dmce_amd.c50 unsigned int bank; member
87 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) in lvt_interrupt_supported() argument
92 if (bank == 4) in lvt_interrupt_supported()
109 b->bank, b->block, b->address, hi, lo); in lvt_off_valid()
116 b->cpu, apic, b->bank, b->block, b->address, hi, lo); in lvt_off_valid()
199 unsigned int bank, block; in mce_amd_feature_init() local
202 for (bank = 0; bank < NR_BANKS; ++bank) { in mce_amd_feature_init()
205 address = MSR_IA32_MC0_MISC + bank * 4; in mce_amd_feature_init()
226 per_cpu(bank_map, cpu) |= (1 << bank); in mce_amd_feature_init()
227 if (shared_bank[bank] && c->cpu_core_id) in mce_amd_feature_init()
[all …]
/arch/arm/mach-omap2/
Dirq.c81 static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg) in intc_bank_write_reg() argument
83 __raw_writel(val, bank->base_reg + reg); in intc_bank_write_reg()
86 static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg) in intc_bank_read_reg() argument
88 return __raw_readl(bank->base_reg + reg); in intc_bank_read_reg()
103 static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank) in omap_irq_bank_init_one() argument
107 tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff; in omap_irq_bank_init_one()
110 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs); in omap_irq_bank_init_one()
112 tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG); in omap_irq_bank_init_one()
114 intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG); in omap_irq_bank_init_one()
116 while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1)) in omap_irq_bank_init_one()
[all …]
Dpowerdomain-common.c51 u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank) in omap2_pwrdm_get_mem_bank_onstate_mask() argument
53 switch (bank) { in omap2_pwrdm_get_mem_bank_onstate_mask()
71 u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank) in omap2_pwrdm_get_mem_bank_retst_mask() argument
73 switch (bank) { in omap2_pwrdm_get_mem_bank_retst_mask()
91 u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank) in omap2_pwrdm_get_mem_bank_stst_mask() argument
93 switch (bank) { in omap2_pwrdm_get_mem_bank_stst_mask()
Dpowerdomain2xxx_3xxx.c51 static int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, in omap2_pwrdm_set_mem_onst() argument
56 m = omap2_pwrdm_get_mem_bank_onstate_mask(bank); in omap2_pwrdm_set_mem_onst()
64 static int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, in omap2_pwrdm_set_mem_retst() argument
69 m = omap2_pwrdm_get_mem_bank_retst_mask(bank); in omap2_pwrdm_set_mem_retst()
77 static int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) in omap2_pwrdm_read_mem_pwrst() argument
81 m = omap2_pwrdm_get_mem_bank_stst_mask(bank); in omap2_pwrdm_read_mem_pwrst()
87 static int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) in omap2_pwrdm_read_mem_retst() argument
91 m = omap2_pwrdm_get_mem_bank_retst_mask(bank); in omap2_pwrdm_read_mem_retst()
164 static int omap3_get_mem_bank_lastmemst_mask(u8 bank) in omap3_get_mem_bank_lastmemst_mask() argument
166 switch (bank) { in omap3_get_mem_bank_lastmemst_mask()
[all …]
Dpowerdomain.h157 int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
158 int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
162 int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
163 int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
164 int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank);
199 int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
200 int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
205 int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
206 int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
207 int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
[all …]
/arch/mips/sgi-ip22/
Dip22-mc.c37 static inline unsigned int get_bank_config(int bank) in get_bank_config() argument
39 unsigned int res = bank > 1 ? sgimc->mconfig1 : sgimc->mconfig0; in get_bank_config()
40 return bank % 2 ? res & 0xffff : res >> 16; in get_bank_config()
54 struct mem bank[4]; in probe_memory() local
58 for (i = 0; i < ARRAY_SIZE(bank); i++) { in probe_memory()
63 bank[cnt].size = get_bank_size(tmp); in probe_memory()
64 bank[cnt].addr = get_bank_addr(tmp); in probe_memory()
66 i, bank[cnt].size / 1024 / 1024, bank[cnt].addr); in probe_memory()
76 if (bank[i-1].addr > bank[i].addr) { in probe_memory()
77 addr = bank[i].addr; in probe_memory()
[all …]
/arch/xtensa/mm/
Dinit.c61 if (start < sysmem.bank[i].end in mem_reserve()
62 && end >= sysmem.bank[i].start) in mem_reserve()
72 if (start > sysmem.bank[i].start) { in mem_reserve()
73 if (end < sysmem.bank[i].end) { in mem_reserve()
77 sysmem.bank[sysmem.nr_banks].start = end; in mem_reserve()
78 sysmem.bank[sysmem.nr_banks].end = sysmem.bank[i].end; in mem_reserve()
81 sysmem.bank[i].end = start; in mem_reserve()
83 if (end < sysmem.bank[i].end) in mem_reserve()
84 sysmem.bank[i].start = end; in mem_reserve()
88 sysmem.bank[i].start = sysmem.bank[sysmem.nr_banks].start; in mem_reserve()
[all …]
/arch/mips/sgi-ip32/
Dip32-memory.c25 int bank; in prom_meminit() local
29 for (bank=0; bank < CRIME_MAXBANKS; bank++) { in prom_meminit()
30 u64 bankctl = crime->bank_ctrl[bank]; in prom_meminit()
32 if (bank != 0 && base == 0) in prom_meminit()
40 bank, base, size >> 20); in prom_meminit()
/arch/arm/mach-omap1/
Dirq.c65 static inline unsigned int irq_bank_readl(int bank, int offset) in irq_bank_readl() argument
67 return omap_readl(irq_banks[bank].base_reg + offset); in irq_bank_readl()
70 static inline void irq_bank_writel(unsigned long value, int bank, int offset) in irq_bank_writel() argument
72 omap_writel(value, irq_banks[bank].base_reg + offset); in irq_bank_writel()
85 int bank = IRQ_BANK(d->irq); in omap_mask_irq() local
88 l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); in omap_mask_irq()
90 omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); in omap_mask_irq()
95 int bank = IRQ_BANK(d->irq); in omap_unmask_irq() local
98 l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); in omap_unmask_irq()
100 omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET); in omap_unmask_irq()
[all …]
/arch/arm/mach-msm/
Dboard-trout-gpio.c116 int bank = TROUT_INT_TO_BANK(d->irq); in trout_gpio_irq_ack() local
118 int reg = TROUT_BANK_TO_STAT_REG(bank); in trout_gpio_irq_ack()
127 int bank = TROUT_INT_TO_BANK(d->irq); in trout_gpio_irq_mask() local
129 int reg = TROUT_BANK_TO_MASK_REG(bank); in trout_gpio_irq_mask()
132 reg_val = trout_int_mask[bank] |= mask; in trout_gpio_irq_mask()
143 int bank = TROUT_INT_TO_BANK(d->irq); in trout_gpio_irq_unmask() local
145 int reg = TROUT_BANK_TO_MASK_REG(bank); in trout_gpio_irq_unmask()
148 reg_val = trout_int_mask[bank] &= ~mask; in trout_gpio_irq_unmask()
158 int bank = TROUT_INT_TO_BANK(d->irq); in trout_gpio_irq_set_wake() local
163 trout_sleep_int_mask[bank] &= ~mask; in trout_gpio_irq_set_wake()
[all …]
Dboard-mahimahi.c60 mi->bank[0].start = PHYS_OFFSET; in mahimahi_fixup()
61 mi->bank[0].node = PHYS_TO_NID(PHYS_OFFSET); in mahimahi_fixup()
62 mi->bank[0].size = (219*1024*1024); in mahimahi_fixup()
63 mi->bank[1].start = MSM_HIGHMEM_BASE; in mahimahi_fixup()
64 mi->bank[1].node = PHYS_TO_NID(MSM_HIGHMEM_BASE); in mahimahi_fixup()
65 mi->bank[1].size = MSM_HIGHMEM_SIZE; in mahimahi_fixup()
Dboard-sapphire.c84 mi->bank[0].start = PHYS_OFFSET; in sapphire_fixup()
85 mi->bank[0].node = PHYS_TO_NID(PHYS_OFFSET); in sapphire_fixup()
87 mi->bank[0].size = (84*1024*1024); in sapphire_fixup()
89 mi->bank[0].size = (101*1024*1024); in sapphire_fixup()
93 mi->bank[0].size = (101*1024*1024); in sapphire_fixup()
/arch/arm/include/asm/
Dsetup.h205 struct membank bank[NR_BANKS]; member
213 #define bank_pfn_start(bank) __phys_to_pfn((bank)->start) argument
214 #define bank_pfn_end(bank) __phys_to_pfn((bank)->start + (bank)->size) argument
215 #define bank_pfn_size(bank) ((bank)->size >> PAGE_SHIFT) argument
216 #define bank_phys_start(bank) (bank)->start argument
217 #define bank_phys_end(bank) ((bank)->start + (bank)->size) argument
218 #define bank_phys_size(bank) (bank)->size argument
/arch/blackfin/kernel/
Dbfin_gpio.c594 u16 bank, mask, i; in bfin_pm_standby_ctrl() local
598 bank = gpio_bank(i); in bfin_pm_standby_ctrl()
601 bfin_internal_set_wake(sic_iwr_irqs[bank], ctrl); in bfin_pm_standby_ctrl()
608 int i, bank; in bfin_gpio_pm_hibernate_suspend() local
616 bank = gpio_bank(i); in bfin_gpio_pm_hibernate_suspend()
619 gpio_bank_saved[bank].fer = *port_fer[bank]; in bfin_gpio_pm_hibernate_suspend()
621 gpio_bank_saved[bank].mux = *port_mux[bank]; in bfin_gpio_pm_hibernate_suspend()
623 if (bank == 0) in bfin_gpio_pm_hibernate_suspend()
624 gpio_bank_saved[bank].mux = bfin_read_PORT_MUX(); in bfin_gpio_pm_hibernate_suspend()
627 gpio_bank_saved[bank].data = gpio_array[bank]->data; in bfin_gpio_pm_hibernate_suspend()
[all …]
/arch/unicore32/mm/
Dinit.c73 struct membank *bank = &mi->bank[i]; in show_mem() local
77 pfn1 = bank_pfn_start(bank); in show_mem()
78 pfn2 = bank_pfn_end(bank); in show_mem()
117 struct membank *bank = &mi->bank[i]; in find_limits() local
120 start = bank_pfn_start(bank); in find_limits()
121 end = bank_pfn_end(bank); in find_limits()
127 if (bank->highmem) in find_limits()
249 sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), in uc32_memblock_init()
253 memblock_add(mi->bank[i].start, mi->bank[i].size); in uc32_memblock_init()
377 struct membank *bank = &mi->bank[i]; in free_unused_memmap() local
[all …]
/arch/arm/mach-clps711x/
Dedb7211-arch.c50 mi->bank[0].start = 0xc0000000; in fixup_edb7211()
51 mi->bank[0].size = 8*1024*1024; in fixup_edb7211()
52 mi->bank[1].start = 0xc1000000; in fixup_edb7211()
53 mi->bank[1].size = 8*1024*1024; in fixup_edb7211()
/arch/mips/jz4740/
Dsetup.c34 u32 ctrl, bus, bank, rows, cols; in jz4740_detect_mem() local
40 bank = 1 + ((ctrl >> 19) & 1); in jz4740_detect_mem()
45 bus, bank, rows, cols); in jz4740_detect_mem()
48 size = 1 << (bus + bank + cols + rows); in jz4740_detect_mem()
/arch/blackfin/mach-common/
Dints-priority.c218 u32 bank, bit, wakeup = 0; in bfin_internal_set_wake() local
220 bank = SIC_SYSIRQ(irq) / 32; in bfin_internal_set_wake()
256 bfin_sic_iwr[bank] |= (1 << bit); in bfin_internal_set_wake()
260 bfin_sic_iwr[bank] &= ~(1 << bit); in bfin_internal_set_wake()
657 inline unsigned int get_irq_base(u32 bank, u8 bmap) in get_irq_base() argument
661 if (bank < 2) { /*PA-PB */ in get_irq_base()
673 u16 bank, bit, irq_base, bit_pos; in init_pint_lut() local
679 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) { in init_pint_lut()
681 pint_assign = pint[bank]->assign; in init_pint_lut()
687 irq_base = get_irq_base(bank, bmap); in init_pint_lut()
[all …]
/arch/alpha/kernel/
Dsys_ruffian.c183 unsigned long bank_addr, bank, ret = 0; in ruffian_get_bank_size() local
188 bank = *(vulp)bank_addr; in ruffian_get_bank_size()
191 if (bank & 0x01) { in ruffian_get_bank_size()
204 bank = (bank & 0x1e) >> 1; in ruffian_get_bank_size()
205 if (bank < ARRAY_SIZE(size)) in ruffian_get_bank_size()
206 ret = size[bank]; in ruffian_get_bank_size()
/arch/x86/platform/scx200/
Dscx200_32.c50 int bank; in scx200_init_shadow() local
53 for (bank = 0; bank < 2; ++bank) in scx200_init_shadow()
54 scx200_gpio_shadow[bank] = inl(scx200_gpio_base + 0x10 * bank); in scx200_init_shadow()

123456789