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Searched refs:bus_clk (Results 1 – 4 of 4) sorted by relevance

/arch/mips/ar7/
Dclock.c100 static struct clk bus_clk = { variable
222 int base_clock = bus_clk.rate; in tnetd7300_set_clock()
226 base_clock = bus_clk.rate; in tnetd7300_set_clock()
257 bus_clk.rate = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT, in tnetd7300_init_clocks()
264 cpu_clk.rate = bus_clk.rate; in tnetd7300_init_clocks()
353 bus_clk.rate = in tnetd7200_init_clocks()
357 bus_clk.rate); in tnetd7200_init_clocks()
384 bus_clk.rate = cpu_clk.rate / 2; in tnetd7200_init_clocks()
387 dsp_mul * 2, bus_clk.rate); in tnetd7200_init_clocks()
394 bus_clk.rate = ((dsp_base / dsp_prediv) * dsp_mul) in tnetd7200_init_clocks()
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Dplatform.c569 struct clk *bus_clk; in ar7_register_uarts() local
574 bus_clk = clk_get(NULL, "bus"); in ar7_register_uarts()
575 if (IS_ERR(bus_clk)) in ar7_register_uarts()
579 uart_port.uartclk = clk_get_rate(bus_clk) / 2; in ar7_register_uarts()
/arch/sh/kernel/cpu/
Dclock-cpg.c18 static struct clk bus_clk = { variable
34 &bus_clk,
42 CLKDEV_CON_ID("bus_clk", &bus_clk),
/arch/powerpc/sysdev/
Dmv64x60_dev.c406 pdata.bus_clk = *prop / 1000000; /* wdt driver wants freq in MHz */ in mv64x60_wdt_device_setup()