| /arch/arm/mach-msm/ |
| D | smd.c | 150 static int smd_stream_read_avail(struct smd_channel *ch) in smd_stream_read_avail() argument
152 return (ch->recv->head - ch->recv->tail) & ch->fifo_mask; in smd_stream_read_avail()
156 static int smd_stream_write_avail(struct smd_channel *ch) in smd_stream_write_avail() argument
158 return ch->fifo_mask - in smd_stream_write_avail()
159 ((ch->send->head - ch->send->tail) & ch->fifo_mask); in smd_stream_write_avail()
162 static int smd_packet_read_avail(struct smd_channel *ch) in smd_packet_read_avail() argument
164 if (ch->current_packet) { in smd_packet_read_avail()
165 int n = smd_stream_read_avail(ch); in smd_packet_read_avail()
166 if (n > ch->current_packet) in smd_packet_read_avail()
167 n = ch->current_packet; in smd_packet_read_avail()
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| D | smd_private.h | 301 int (*read)(struct smd_channel *ch, void *data, int len);
302 int (*write)(struct smd_channel *ch, const void *data, int len);
303 int (*read_avail)(struct smd_channel *ch);
304 int (*write_avail)(struct smd_channel *ch);
306 void (*update_state)(struct smd_channel *ch);
343 static inline int _smd_alloc_channel(struct smd_channel *ch) in _smd_alloc_channel() argument
347 shared1 = smem_alloc(ID_SMD_CHANNELS + ch->n, sizeof(*shared1)); in _smd_alloc_channel()
349 pr_err("smd_alloc_channel() cid %d does not exist\n", ch->n); in _smd_alloc_channel()
352 ch->send = &shared1->ch0; in _smd_alloc_channel()
353 ch->recv = &shared1->ch1; in _smd_alloc_channel()
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| /arch/arm/mach-tegra/ |
| D | dma.c | 141 static void tegra_dma_update_hw(struct tegra_dma_channel *ch,
143 static void tegra_dma_update_hw_partial(struct tegra_dma_channel *ch,
145 static void tegra_dma_stop(struct tegra_dma_channel *ch);
147 void tegra_dma_flush(struct tegra_dma_channel *ch) in tegra_dma_flush() argument
152 void tegra_dma_dequeue(struct tegra_dma_channel *ch) in tegra_dma_dequeue() argument
156 if (tegra_dma_is_empty(ch)) in tegra_dma_dequeue()
159 req = list_entry(ch->list.next, typeof(*req), node); in tegra_dma_dequeue()
161 tegra_dma_dequeue_req(ch, req); in tegra_dma_dequeue()
165 static void tegra_dma_stop(struct tegra_dma_channel *ch) in tegra_dma_stop() argument
170 csr = readl(ch->addr + APB_DMA_CHAN_CSR); in tegra_dma_stop()
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| /arch/arm/mach-msm/include/mach/ |
| D | dma.h | 49 #define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2)) argument
50 #define DMOV_SD1(off, ch) (MSM_DMOV_BASE + 0x0400 + (off) + ((ch) << 2)) argument
51 #define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2)) argument
52 #define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2)) argument
60 #define DMOV_CMD_PTR(ch) DMOV_SD_AARM(0x000, ch) argument
67 #define DMOV_RSLT(ch) DMOV_SD_AARM(0x040, ch) argument
74 #define DMOV_FLUSH0(ch) DMOV_SD_AARM(0x080, ch) argument
75 #define DMOV_FLUSH1(ch) DMOV_SD_AARM(0x0C0, ch) argument
76 #define DMOV_FLUSH2(ch) DMOV_SD_AARM(0x100, ch) argument
77 #define DMOV_FLUSH3(ch) DMOV_SD_AARM(0x140, ch) argument
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| D | msm_smd.h | 25 int smd_open(const char *name, smd_channel_t **ch, void *priv,
32 int smd_close(smd_channel_t *ch);
35 int smd_read(smd_channel_t *ch, void *data, int len);
42 int smd_write(smd_channel_t *ch, const void *data, int len);
43 int smd_write_atomic(smd_channel_t *ch, const void *data, int len);
45 int smd_write_avail(smd_channel_t *ch);
46 int smd_read_avail(smd_channel_t *ch);
51 int smd_cur_packet_size(smd_channel_t *ch);
57 void smd_kick(smd_channel_t *ch);
64 int smd_wait_until_readable(smd_channel_t *ch, int bytes);
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| /arch/x86/boot/ |
| D | ctype.h | 5 static inline int isdigit(int ch) in isdigit() argument
7 return (ch >= '0') && (ch <= '9'); in isdigit()
10 static inline int isxdigit(int ch) in isxdigit() argument
12 if (isdigit(ch)) in isxdigit()
15 if ((ch >= 'a') && (ch <= 'f')) in isxdigit()
18 return (ch >= 'A') && (ch <= 'F'); in isxdigit()
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| D | tty.c | 30 static void __attribute__((section(".inittext"))) serial_putchar(int ch) in serial_putchar() argument
37 outb(ch, early_serial_base + TXR); in serial_putchar()
40 static void __attribute__((section(".inittext"))) bios_putchar(int ch) in bios_putchar() argument
48 ireg.al = ch; in bios_putchar()
52 void __attribute__((section(".inittext"))) putchar(int ch) in putchar() argument
54 if (ch == '\n') in putchar()
57 bios_putchar(ch); in putchar()
60 serial_putchar(ch); in putchar()
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| /arch/mips/include/asm/txx9/ |
| D | tx3927.h | 20 #define TX3927_TMR_REG(ch) (TX3927_REG_BASE + 0xf000 + (ch) * 0x100) argument
22 #define TX3927_SIO_REG(ch) (TX3927_REG_BASE + 0xf300 + (ch) * 0x100) argument
46 } ch[4]; member
162 #define TX3927_DMA_MCR_EIS(ch) (0x10000000<<(ch)) argument
163 #define TX3927_DMA_MCR_DIS(ch) (0x01000000<<(ch)) argument
165 #define TX3927_DMA_MCR_FIFUM(ch) (0x00000008<<(ch)) argument
221 #define TX3927_IR_SIO(ch) (6 + (ch)) argument
225 #define TX3927_IR_TMR(ch) (13 + (ch)) argument
298 #define TX3927_PCFG_SDRCLKEN(ch) (0x00400000<<(ch)) argument
300 #define TX3927_PCFG_PCICLKEN(ch) (0x00040000<<(ch)) argument
[all …]
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| D | tx4938.h | 31 #define TX4938_DMA_REG(ch) (TX4938_REG_BASE + 0xb000 + (ch) * 0x800) argument
35 #define TX4938_TMR_REG(ch) ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100) argument
37 #define TX4938_SIO_REG(ch) ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100) argument
73 #define TX4938_IR_DMA(ch, n) ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */ argument
147 #define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch)) argument
149 #define TX4938_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) argument
200 #define TX4938_DMA_MCR_EIS(ch) (0x10000000<<(ch)) argument
201 #define TX4938_DMA_MCR_DIS(ch) (0x01000000<<(ch)) argument
203 #define TX4938_DMA_MCR_FIFUM(ch) (0x00000008<<(ch)) argument
270 #define TX4938_SDRAMC_CR(ch) TX4927_SDRAMC_CR(ch) argument
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| D | tx4927.h | 49 #define TX4927_TMR_REG(ch) (TX4927_REG_BASE + 0xf000 + (ch) * 0x100) argument
51 #define TX4927_SIO_REG(ch) (TX4927_REG_BASE + 0xf300 + (ch) * 0x100) argument
142 #define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch)) argument
144 #define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) argument
203 #define TX4927_SDRAMC_CR(ch) __raw_readq(&tx4927_sdramcptr->cr[(ch)]) argument
204 #define TX4927_SDRAMC_BA(ch) ((TX4927_SDRAMC_CR(ch) >> 49) << 21) argument
205 #define TX4927_SDRAMC_SIZE(ch) \ argument
206 ((((TX4927_SDRAMC_CR(ch) >> 33) & 0x7fff) + 1) << 21)
208 #define TX4927_EBUSC_CR(ch) __raw_readq(&tx4927_ebuscptr->cr[(ch)]) argument
209 #define TX4927_EBUSC_BA(ch) ((TX4927_EBUSC_CR(ch) >> 48) << 20) argument
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| /arch/mips/lantiq/xway/ |
| D | dma.c | 68 ltq_dma_enable_irq(struct ltq_dma_channel *ch) in ltq_dma_enable_irq() argument
73 ltq_dma_w32(ch->nr, LTQ_DMA_CS); in ltq_dma_enable_irq()
74 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); in ltq_dma_enable_irq()
80 ltq_dma_disable_irq(struct ltq_dma_channel *ch) in ltq_dma_disable_irq() argument
85 ltq_dma_w32(ch->nr, LTQ_DMA_CS); in ltq_dma_disable_irq()
86 ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN); in ltq_dma_disable_irq()
92 ltq_dma_ack_irq(struct ltq_dma_channel *ch) in ltq_dma_ack_irq() argument
97 ltq_dma_w32(ch->nr, LTQ_DMA_CS); in ltq_dma_ack_irq()
104 ltq_dma_open(struct ltq_dma_channel *ch) in ltq_dma_open() argument
109 ltq_dma_w32(ch->nr, LTQ_DMA_CS); in ltq_dma_open()
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| /arch/arm/plat-samsung/ |
| D | s3c-dma-ops.c | 24 unsigned ch; member
49 data->ch = dma_ch; in s3c_dma_request()
62 static int s3c_dma_release(unsigned ch, struct s3c2410_dma_client *client) in s3c_dma_release() argument
67 if (data->ch == ch) in s3c_dma_release()
71 s3c2410_dma_free(ch, client); in s3c_dma_release()
77 static int s3c_dma_prepare(unsigned ch, struct samsung_dma_prep_info *info) in s3c_dma_prepare() argument
83 if (data->ch == ch) in s3c_dma_prepare()
87 s3c2410_dma_set_buffdone_fn(ch, s3c_dma_cb); in s3c_dma_prepare()
92 s3c2410_dma_enqueue(ch, (void *)data, info->buf, len); in s3c_dma_prepare()
97 static inline int s3c_dma_trigger(unsigned ch) in s3c_dma_trigger() argument
[all …]
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| /arch/mips/include/asm/mach-rc32434/ |
| D | dma_v.h | 25 static inline int rc32434_halt_dma(struct dma_reg *ch) in rc32434_halt_dma() argument
28 if (__raw_readl(&ch->dmac) & DMA_CHAN_RUN_BIT) { in rc32434_halt_dma()
29 __raw_writel(0, &ch->dmac); in rc32434_halt_dma()
31 if (__raw_readl(&ch->dmas) & DMA_STAT_HALT) { in rc32434_halt_dma()
32 __raw_writel(0, &ch->dmas); in rc32434_halt_dma()
41 static inline void rc32434_start_dma(struct dma_reg *ch, u32 dma_addr) in rc32434_start_dma() argument
43 __raw_writel(0, &ch->dmandptr); in rc32434_start_dma()
44 __raw_writel(dma_addr, &ch->dmadptr); in rc32434_start_dma()
47 static inline void rc32434_chain_dma(struct dma_reg *ch, u32 dma_addr) in rc32434_chain_dma() argument
49 __raw_writel(dma_addr, &ch->dmandptr); in rc32434_chain_dma()
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| /arch/mn10300/kernel/ |
| D | mn10300-debug.c | 22 char ch; in debug_to_serial_mnser() local
25 ch = *p++; in debug_to_serial_mnser()
29 SC0TXB = ch; in debug_to_serial_mnser()
31 if (ch == 0x0a) { in debug_to_serial_mnser()
38 SC1TXB = ch; in debug_to_serial_mnser()
40 if (ch == 0x0a) { in debug_to_serial_mnser()
47 SC2TXB = ch; in debug_to_serial_mnser()
49 if (ch == 0x0a) { in debug_to_serial_mnser()
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| D | gdb-stub.c | 179 static int hex(unsigned char ch);
189 static int hex(unsigned char ch) in hex() argument
191 if (ch >= 'a' && ch <= 'f') in hex()
192 return ch - 'a' + 10; in hex()
193 if (ch >= '0' && ch <= '9') in hex()
194 return ch - '0'; in hex()
195 if (ch >= 'A' && ch <= 'F') in hex()
196 return ch - 'A' + 10; in hex()
237 unsigned char ch; in getpacket() local
246 gdbstub_io_rx_char(&ch, 0); in getpacket()
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| /arch/mips/include/asm/mach-lantiq/xway/ |
| D | xway_dma.h | 50 extern void ltq_dma_enable_irq(struct ltq_dma_channel *ch);
51 extern void ltq_dma_disable_irq(struct ltq_dma_channel *ch);
52 extern void ltq_dma_ack_irq(struct ltq_dma_channel *ch);
53 extern void ltq_dma_open(struct ltq_dma_channel *ch);
54 extern void ltq_dma_close(struct ltq_dma_channel *ch);
55 extern void ltq_dma_alloc_tx(struct ltq_dma_channel *ch);
56 extern void ltq_dma_alloc_rx(struct ltq_dma_channel *ch);
57 extern void ltq_dma_free(struct ltq_dma_channel *ch);
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| /arch/unicore32/include/mach/ |
| D | regs-dmac.h | 38 #define DMAC_SRCADDR(ch) (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x00) argument
42 #define DMAC_DESTADDR(ch) (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x04) argument
46 #define DMAC_CONTROL(ch) (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x0C) argument
50 #define DMAC_CONFIG(ch) (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x10) argument
56 #define DMAC_CHANNEL(ch) FIELD(1, 1, (ch)) argument
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| D | dma.h | 38 static inline void puv3_stop_dma(int ch) in puv3_stop_dma() argument
40 writel(readl(DMAC_CONFIG(ch)) & ~DMAC_CONFIG_EN, DMAC_CONFIG(ch)); in puv3_stop_dma()
43 static inline void puv3_resume_dma(int ch) in puv3_resume_dma() argument
45 writel(readl(DMAC_CONFIG(ch)) | DMAC_CONFIG_EN, DMAC_CONFIG(ch)); in puv3_resume_dma()
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| /arch/sh/kernel/ |
| D | process_64.c | 39 unsigned long long ah, al, bh, bl, ch, cl; in show_regs() local
47 ch = (regs->regs[15]) >> 32; in show_regs()
50 ah, al, bh, bl, ch, cl); in show_regs()
58 asm volatile ("getcon " __KCR0 ", %0" : "=r" (ch)); in show_regs()
60 ch = (ch) >> 32; in show_regs()
63 ah, al, bh, bl, ch, cl); in show_regs()
69 ch = (regs->regs[2]) >> 32; in show_regs()
72 ah, al, bh, bl, ch, cl); in show_regs()
78 ch = (regs->regs[5]) >> 32; in show_regs()
81 ah, al, bh, bl, ch, cl); in show_regs()
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| /arch/sh/lib64/ |
| D | dbg.c | 141 unsigned long long ah, al, bh, bl, ch, cl; in show_excp_regs() local
155 asm volatile ("getcon " __INTEVT ", %0":"=r"(ch)); in show_excp_regs()
157 ch = (ch) >> 32; in show_excp_regs()
160 ah, al, bh, bl, ch, cl); in show_excp_regs()
170 asm volatile ("getcon " __PSSR ", %0":"=r"(ch)); in show_excp_regs()
172 ch = (ch) >> 32; in show_excp_regs()
175 ah, al, bh, bl, ch, cl); in show_excp_regs()
181 ch = (regs->regs[15]) >> 32; in show_excp_regs()
184 ah, al, bh, bl, ch, cl); in show_excp_regs()
192 asm volatile ("getcon " __KCR0 ", %0":"=r"(ch)); in show_excp_regs()
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| /arch/arm/plat-samsung/include/plat/ |
| D | dma-ops.h | 39 unsigned (*request)(enum dma_ch ch, struct samsung_dma_info *info);
40 int (*release)(unsigned ch, struct s3c2410_dma_client *client);
41 int (*prepare)(unsigned ch, struct samsung_dma_prep_info *info);
42 int (*trigger)(unsigned ch);
43 int (*started)(unsigned ch);
44 int (*flush)(unsigned ch);
45 int (*stop)(unsigned ch);
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| /arch/powerpc/platforms/cell/ |
| D | beat_udbg.c | 51 char ch, *buf = (char *)inbuf; in udbg_getc_poll_beat() local
67 ch = buf[0]; in udbg_getc_poll_beat()
71 return ch; in udbg_getc_poll_beat()
76 int ch; in udbg_getc_beat() local
78 ch = udbg_getc_poll_beat(); in udbg_getc_beat()
79 if (ch == -1) { in udbg_getc_beat()
85 return ch; in udbg_getc_beat()
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| /arch/mn10300/boot/compressed/ |
| D | misc.c | 128 unsigned char ch = inptr < insize ? inbuf[inptr++] : fill_inbuf(); in get_byte() local
132 hex[0] = ((ch & 0x0f) > 9) ? in get_byte()
133 ((ch & 0x0f) + 'A' - 0xa) : ((ch & 0x0f) + '0'); in get_byte()
134 hex[1] = ((ch >> 4) > 9) ? in get_byte()
135 ((ch >> 4) + 'A' - 0xa) : ((ch >> 4) + '0'); in get_byte()
139 return ch; in get_byte()
182 static inline void kputchar(unsigned char ch) in kputchar() argument
188 if (ch == 0x0a) { in kputchar()
194 SC0TXB = ch; in kputchar()
200 if (ch == 0x0a) { in kputchar()
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| /arch/arm/boot/compressed/ |
| D | misc.c | 34 static void icedcc_putc(int ch) in icedcc_putc() argument
45 asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch)); in icedcc_putc()
51 static void icedcc_putc(int ch) in icedcc_putc() argument
62 asm("mcr p14, 0, %0, c8, c0, 0" : : "r" (ch)); in icedcc_putc()
67 static void icedcc_putc(int ch) in icedcc_putc() argument
78 asm("mcr p14, 0, %0, c1, c0, 0" : : "r" (ch)); in icedcc_putc()
83 #define putc(ch) icedcc_putc(ch) argument
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| /arch/frv/kernel/ |
| D | uaccess.c | 23 char *p, ch; in strncpy_from_user() local
46 __get_user_asm(err, ch, src, "ub", "=r"); in strncpy_from_user()
49 if (!ch) in strncpy_from_user()
51 *p = ch; in strncpy_from_user()
76 char ch; in strnlen_user() local
89 __get_user_asm(err, ch, p, "ub", "=r"); in strnlen_user()
92 if (!ch) in strnlen_user()
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