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Searched refs:chipcHw_REG_DDR_PHASE_ALIGNED (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-bcmring/include/mach/csp/
DchipcHw_reg.h494 #define chipcHw_REG_DDR_PHASE_ALIGNED 0x00800000 /* DDR Phase aligned status */ macro
DchipcHw_inline.h1478 PhaseAlignStatus & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0; in chipcHw_isDdrHwPhaseAligned()