Searched refs:chipcHw_REG_DDR_PHASE_VALUE_LE_MASK (Results 1 – 2 of 2) sorted by relevance
477 #define chipcHw_REG_DDR_PHASE_VALUE_LE_MASK 0x0000007F /* DDR upper threshold for phase… macro
1412 || (chipcHw_REG_DDR_PHASE_VALUE_LE_MASK << in chipcHw_setDdrHwPhaseAlignMargin()