Home
last modified time | relevance | path

Searched refs:clk_ctrl (Results 1 – 7 of 7) sorted by relevance

/arch/sparc/kernel/
Dtadpole.c20 static volatile unsigned char *clk_ctrl; variable
41 "r" (clk_ctrl) : in clk_init()
55 "r" (clk_ctrl) : in clk_slow()
67 if (!clk_ctrl) in tsu_clockstop()
76 if (!(clk_ctrl[2] & 1)) in tsu_clockstop()
96 if (!clk_ctrl) in swift_clockstop()
98 clk_ctrl[0] = 0; in swift_clockstop()
116 clk_ctrl = (char *) prom_getint(clk_nd, "address"); in clock_stop_probe()
/arch/cris/arch-v32/mach-fs/
Dcpufreq.c25 reg_config_rw_clk_ctrl clk_ctrl; in cris_freq_get_cpu_frequency() local
26 clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl); in cris_freq_get_cpu_frequency()
27 return clk_ctrl.pll ? 200000 : 6000; in cris_freq_get_cpu_frequency()
34 reg_config_rw_clk_ctrl clk_ctrl; in cris_freq_set_cpu_state() local
35 clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl); in cris_freq_set_cpu_state()
50 clk_ctrl.pll = 1; in cris_freq_set_cpu_state()
52 clk_ctrl.pll = 0; in cris_freq_set_cpu_state()
53 REG_WR(config, regi_config, rw_clk_ctrl, clk_ctrl); in cris_freq_set_cpu_state()
Ddma.c24 reg_config_rw_clk_ctrl clk_ctrl; in crisv32_request_dma() local
49 clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl); in crisv32_request_dma()
55 clk_ctrl.dma01_eth0 = 1; in crisv32_request_dma()
59 clk_ctrl.dma23 = 1; in crisv32_request_dma()
63 clk_ctrl.dma45 = 1; in crisv32_request_dma()
67 clk_ctrl.dma67 = 1; in crisv32_request_dma()
71 clk_ctrl.dma89_strcop = 1; in crisv32_request_dma()
218 REG_WR(config, regi_config, rw_clk_ctrl, clk_ctrl); in crisv32_request_dma()
/arch/cris/arch-v32/mach-a3/
Dcpufreq.c25 reg_clkgen_rw_clk_ctrl clk_ctrl; in cris_freq_get_cpu_frequency() local
26 clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); in cris_freq_get_cpu_frequency()
27 return clk_ctrl.pll ? 200000 : 6000; in cris_freq_get_cpu_frequency()
34 reg_clkgen_rw_clk_ctrl clk_ctrl; in cris_freq_set_cpu_state() local
35 clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); in cris_freq_set_cpu_state()
53 clk_ctrl.pll = 1; in cris_freq_set_cpu_state()
55 clk_ctrl.pll = 0; in cris_freq_set_cpu_state()
56 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl); in cris_freq_set_cpu_state()
Ddma.c23 reg_clkgen_rw_clk_ctrl clk_ctrl; in crisv32_request_dma() local
47 clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); in crisv32_request_dma()
53 clk_ctrl.dma0_1_eth = 1; in crisv32_request_dma()
57 clk_ctrl.dma2_3_strcop = 1; in crisv32_request_dma()
61 clk_ctrl.dma4_5_iop = 1; in crisv32_request_dma()
65 clk_ctrl.sser_ser_dma6_7 = 1; in crisv32_request_dma()
69 clk_ctrl.dma9_11 = 1; in crisv32_request_dma()
173 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl); in crisv32_request_dma()
Dpinmux.c89 reg_clkgen_rw_clk_ctrl clk_ctrl; in crisv32_pinmux_alloc_fixed() local
99 clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); in crisv32_pinmux_alloc_fixed()
103 clk_ctrl.eth = regk_clkgen_yes; in crisv32_pinmux_alloc_fixed()
104 clk_ctrl.dma0_1_eth = regk_clkgen_yes; in crisv32_pinmux_alloc_fixed()
114 clk_ctrl.ccd_tg_100 = clk_ctrl.ccd_tg_200 = regk_clkgen_yes; in crisv32_pinmux_alloc_fixed()
119 clk_ctrl.ccd_tg_100 = clk_ctrl.ccd_tg_200 = regk_clkgen_yes; in crisv32_pinmux_alloc_fixed()
125 clk_ctrl.strdma0_2_video = regk_clkgen_yes; in crisv32_pinmux_alloc_fixed()
130 clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes; in crisv32_pinmux_alloc_fixed()
135 clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes; in crisv32_pinmux_alloc_fixed()
140 clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes; in crisv32_pinmux_alloc_fixed()
[all …]
/arch/cris/boot/compressed/
Dmisc.c291 reg_clkgen_rw_clk_ctrl clk_ctrl; in decompress_kernel() local
295 clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); in decompress_kernel()
296 clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes; in decompress_kernel()
297 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl); in decompress_kernel()