Searched refs:clk_h (Results 1 – 17 of 17) sorted by relevance
| /arch/arm/mach-ep93xx/ |
| D | clock.c | 80 static struct clk clk_h = { variable
142 .parent = &clk_h,
147 .parent = &clk_h,
152 .parent = &clk_h,
157 .parent = &clk_h,
162 .parent = &clk_h,
167 .parent = &clk_h,
172 .parent = &clk_h,
177 .parent = &clk_h,
182 .parent = &clk_h,
[all …]
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| /arch/arm/mach-s3c24xx/ |
| D | common-s3c2443.c | 313 [1] = &clk_h,
447 .parent = &clk_h,
452 .parent = &clk_h,
457 .parent = &clk_h,
462 .parent = &clk_h,
467 .parent = &clk_h,
472 .parent = &clk_h,
482 .parent = &clk_h,
487 .parent = &clk_h,
492 .parent = &clk_h,
[all …]
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| D | clock-s3c2412.c | 145 else if (parent == &clk_h) in s3c2412_setparent_usbsrc()
240 else if (parent == &clk_h) in s3c2412_setparent_armclk()
405 else if (parent == &clk_h) in s3c2412_setparent_cam()
455 .parent = &clk_h,
489 .parent = &clk_h,
494 .parent = &clk_h,
499 .parent = &clk_h,
504 .parent = &clk_h,
509 .parent = &clk_h,
519 .parent = &clk_h,
[all …]
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| D | clock-s3c244x.c | 52 else if (parent == &clk_h) in s3c2440_setparent_armclk()
85 clk_arm.parent = (camdivn & S3C2440_CAMDIVN_DVSEN) ? &clk_h : &clk_f; in s3c244x_clk_add()
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| D | clock-s3c2416.c | 129 .parent = &clk_h,
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| D | mach-rx1950.c | 744 s3c24xx_clkout0.parent = &clk_h; in rx1950_map_io()
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| /arch/arm/mach-s3c64xx/ |
| D | clock.c | 128 .parent = &clk_h,
215 .parent = &clk_h,
220 .parent = &clk_h,
225 .parent = &clk_h,
230 .parent = &clk_h,
235 .parent = &clk_h,
240 .parent = &clk_h,
245 .parent = &clk_h,
250 .parent = &clk_h,
255 .parent = &clk_h,
[all …]
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| /arch/arm/plat-s3c24xx/ |
| D | s3c2410-clock.c | 93 .parent = &clk_h,
127 .parent = &clk_h,
137 .parent = &clk_h,
142 .parent = &clk_h,
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| D | clock.c | 56 clk_h.rate = hclk; in s3c24xx_setup_clocks()
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| D | clock-dclk.c | 138 else if (parent == &clk_h) in s3c24xx_clkout_setparent()
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| /arch/arm/plat-samsung/include/plat/ |
| D | clock.h | 74 extern struct clk clk_h;
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| /arch/arm/plat-samsung/ |
| D | clock.c | 244 struct clk clk_h = { variable
376 if (s3c24xx_register_clock(&clk_h) < 0) in s3c24xx_register_baseclocks()
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| /arch/arm/mach-s5p64x0/ |
| D | clock-s5p6450.c | 213 .parent = &clk_h,
654 clk_h.rate = hclk; in s5p6450_setup_clocks()
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| D | clock-s5p6440.c | 583 clk_h.rate = hclk; in s5p6440_setup_clocks()
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| /arch/arm/mach-s5pc100/ |
| D | clock.c | 1219 clk_h.rate = hclkd1; in s5pc100_setup_clocks()
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| /arch/arm/mach-s5pv210/ |
| D | clock.c | 1302 clk_h.rate = hclk_psys; in s5pv210_setup_clocks()
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| /arch/arm/mach-exynos/ |
| D | clock-exynos4.c | 1515 clk_h.rate = sclk_dmc; in exynos4_setup_clocks()
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