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Searched refs:clrsetbits_be32 (Results 1 – 14 of 14) sorted by relevance

/arch/powerpc/platforms/83xx/
Dusb.c132 clrsetbits_be32(immap + MPC83XX_SCCR_OFFS, in mpc831x_usb_cfg()
136 clrsetbits_be32(immap + MPC83XX_SCCR_OFFS, in mpc831x_usb_cfg()
143 clrsetbits_be32(immap + MPC83XX_SICRH_OFFS, in mpc831x_usb_cfg()
147 clrsetbits_be32(immap + MPC83XX_SICRL_OFFS, in mpc831x_usb_cfg()
150 clrsetbits_be32(immap + MPC83XX_SICRH_OFFS, in mpc831x_usb_cfg()
154 clrsetbits_be32(immap + MPC83XX_SICRL_OFFS, in mpc831x_usb_cfg()
157 clrsetbits_be32(immap + MPC83XX_SICRH_OFFS, in mpc831x_usb_cfg()
243 clrsetbits_be32(immap + MPC83XX_SCCR_OFFS, MPC837X_SCCR_USB_DRCM_11, in mpc837x_usb_cfg()
247 clrsetbits_be32(immap + MPC83XX_SICRL_OFFS, MPC837X_SICRL_USB_MASK, in mpc837x_usb_cfg()
Dmpc837x_rdb.c39 clrsetbits_be32(im + MPC83XX_SICRL_OFFS, MPC837X_SICRL_USBB_MASK, in mpc837x_rdb_sd_cfg()
41 clrsetbits_be32(im + MPC83XX_SICRH_OFFS, MPC837X_SICRH_SPI_MASK, in mpc837x_rdb_sd_cfg()
Dkm83xx.c114 clrsetbits_be32((base + 0xac), 0xff0, 0xaa0); in mpc83xx_km_setup_arch()
Dmpc836x_mds.c132 clrsetbits_be32(immap + 4, 0xff0, 0xaa0); in mpc836x_mds_setup_arch()
/arch/powerpc/sysdev/qe_lib/
Dgpio.c236 clrsetbits_be32(&regs->cpdir2, mask2, sregs->cpdir2 & mask2); in qe_pin_set_dedicated()
237 clrsetbits_be32(&regs->cppar2, mask2, sregs->cppar2 & mask2); in qe_pin_set_dedicated()
239 clrsetbits_be32(&regs->cpdir1, mask2, sregs->cpdir1 & mask2); in qe_pin_set_dedicated()
240 clrsetbits_be32(&regs->cppar1, mask2, sregs->cppar1 & mask2); in qe_pin_set_dedicated()
249 clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1); in qe_pin_set_dedicated()
Dusb.c50 clrsetbits_be32(&mux->cmxgcr, QE_CMXGCR_USBCS, val); in qe_usb_clock_set()
Ducc.c37 clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG, in ucc_set_qe_mux_mii_mng()
209 clrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift, in ucc_set_qe_mux_rxtx()
/arch/powerpc/include/asm/
Dfsl_guts.h128 clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift); in guts_set_dmacr()
165 clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift); in guts_set_pmuxcr_dma()
Dfsl_lbc.h265 clrsetbits_be32(upm->mxmr, MxMR_MAD, MxMR_OP_RP | pat_offset); in fsl_upm_start_pattern()
Dio.h782 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) macro
/arch/powerpc/sysdev/
Dfsl_85xx_l2ctlr.c138 clrsetbits_be32(&l2ctlr->ctl, L2CR_L2E, L2CR_L2FI); in mpc85xx_l2ctlr_of_probe()
Dfsl_lbc.c202 clrsetbits_be32(&lbc->lbcr, LBCR_BMT, LBCR_BMTPS); in fsl_lbc_ctrl_init()
/arch/powerpc/platforms/52xx/
Dmpc52xx_gpt.c304 clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK, r); in mpc52xx_gpt_gpio_set()
354 clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK, in mpc52xx_gpt_gpio_setup()
452 clrsetbits_be32(&gpt->regs->mode, clear, set); in mpc52xx_gpt_do_start()
/arch/powerpc/platforms/85xx/
Dp1022_ds.c356 clrsetbits_be32(&guts->pmuxcr, PMUXCR_ELBCDIU_MASK, in p1022ds_set_monitor_port()