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Searched refs:cond (Results 1 – 25 of 56) sorted by relevance

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/arch/arm/include/asm/
Dunified.h64 .macro it, cond
66 .macro itt, cond
68 .macro ite, cond
70 .macro ittt, cond
72 .macro itte, cond
74 .macro itet, cond
76 .macro itee, cond
78 .macro itttt, cond
80 .macro ittte, cond
82 .macro ittet, cond
[all …]
Dassembler.h108 .macro asm_trace_hardirqs_on_cond, cond
115 bl\cond trace_hardirqs_on
247 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
250 \instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
252 \instr\cond\()\t\().w \reg, [\ptr, #\off]
263 .macro usracc, instr, reg, ptr, inc, cond, rept, abort
266 .ifnc \cond,al
268 itt \cond
270 ittt \cond
277 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
[all …]
Dspinlock.h34 #define WFE(cond) ALT_SMP( \ argument
35 "it " cond "\n\t" \
36 "wfe" cond ".n", \
42 #define WFE(cond) ALT_SMP("wfe" cond, "nop") argument
Dvfpmacros.h11 .macro VFPFMRX, rd, sysreg, cond in toolkits()
12 MRC\cond p10, 7, \rd, \sysreg, cr0, 0 @ FMRX \rd, \sysreg in toolkits()
15 .macro VFPFMXR, sysreg, rd, cond in toolkits()
16 MCR\cond p10, 7, \rd, \sysreg, cr0, 0 @ FMXR \sysreg, \rd in toolkits()
/arch/parisc/math-emu/
Ddfcmp.c51 unsigned int cond, unsigned int *status) in dbl_fcmp() argument
73 && (Exception(cond) || Dbl_isone_signaling(leftp1))) in dbl_fcmp()
77 && (Exception(cond) || Dbl_isone_signaling(rightp1))) ) in dbl_fcmp()
80 Set_status_cbit(Unordered(cond)); in dbl_fcmp()
84 Set_status_cbit(Unordered(cond)); in dbl_fcmp()
96 Set_status_cbit(Unordered(cond)); in dbl_fcmp()
111 Set_status_cbit(Equal(cond)); in dbl_fcmp()
115 Set_status_cbit(Lessthan(cond)); in dbl_fcmp()
119 Set_status_cbit(Greaterthan(cond)); in dbl_fcmp()
126 Set_status_cbit(Equal(cond)); in dbl_fcmp()
[all …]
Dsfcmp.c50 unsigned int cond, unsigned int *status) in sgl_fcmp() argument
73 && (Exception(cond) || Sgl_isone_signaling(left))) in sgl_fcmp()
77 && (Exception(cond) || Sgl_isone_signaling(right)) ) ) in sgl_fcmp()
80 Set_status_cbit(Unordered(cond)); in sgl_fcmp()
84 Set_status_cbit(Unordered(cond)); in sgl_fcmp()
96 Set_status_cbit(Unordered(cond)); in sgl_fcmp()
111 Set_status_cbit(Equal(cond)); in sgl_fcmp()
115 Set_status_cbit(Lessthan(cond)); in sgl_fcmp()
119 Set_status_cbit(Greaterthan(cond)); in sgl_fcmp()
126 Set_status_cbit(Equal(cond)); in sgl_fcmp()
[all …]
Dfloat.h536 #define Unordered(cond) Unorderedbit(cond)
537 #define Equal(cond) Equalbit(cond)
538 #define Lessthan(cond) Lessthanbit(cond)
539 #define Greaterthan(cond) Greaterthanbit(cond)
540 #define Exception(cond) Exceptionbit(cond)
/arch/unicore32/include/asm/
Dassembler.h64 .macro notcond, cond, nexti = .+8
65 .ifc \cond, eq
67 .else; .ifc \cond, ne
69 .else; .ifc \cond, ea
71 .else; .ifc \cond, ub
73 .else; .ifc \cond, fs
75 .else; .ifc \cond, ns
77 .else; .ifc \cond, fv
79 .else; .ifc \cond, nv
81 .else; .ifc \cond, ua
[all …]
/arch/ia64/hp/sim/boot/
Dboot_head.S64 (p6) br.cond.sptk.few static
69 (p6) br.cond.sptk.few stacked
72 (p7) br.cond.sptk.few 1f
78 br.cond.sptk.few rp
80 (p7) br.cond.sptk.few 1f
87 (p7) br.cond.sptk.few 1f
92 br.cond.sptk.few rp
94 (p7) br.cond.sptk.few 1f
112 (p7) br.cond.sptk.few 1f
148 (p7) br.cond.sptk.few 1f
[all …]
/arch/arm/lib/
Dmemcpy.S31 .macro ldr1b ptr reg cond=al abort argument
32 ldr\cond\()b \reg, [\ptr], #1
43 .macro str1b ptr reg cond=al abort argument
44 str\cond\()b \reg, [\ptr], #1
Dcopy_from_user.S59 .macro ldr1b ptr reg cond=al abort argument
60 ldrusr \reg, \ptr, 1, \cond, abort=\abort
71 .macro str1b ptr reg cond=al abort argument
72 str\cond\()b \reg, [\ptr], #1
Dcopy_to_user.S55 .macro ldr1b ptr reg cond=al abort argument
56 ldr\cond\()b \reg, [\ptr], #1
74 .macro str1b ptr reg cond=al abort argument
75 strusr \reg, \ptr, 1, \cond, abort=\abort
/arch/unicore32/lib/
Dcopy_from_user.S56 .macro ldr1b ptr reg cond=al abort argument
57 ldrusr \reg, \ptr, 1, \cond, abort=\abort
68 .macro str1b ptr reg cond=al abort argument
69 .ifnc \cond, al
70 b\cond 201f
Dcopy_to_user.S48 .macro ldr1b ptr reg cond=al abort argument
49 notcond \cond, .+8
65 .macro str1b ptr reg cond=al abort argument
66 strusr \reg, \ptr, 1, \cond, abort=\abort
/arch/arm/boot/compressed/
Ddecompress.c20 # define Assert(cond,msg) {if(!(cond)) error(msg);} argument
27 # define Assert(cond,msg) argument
/arch/ia64/sn/kernel/sn2/
Dptc_deadlock.S54 (p6) br.cond.sptk 5b
69 (p6) br.cond.sptk 5b;;
80 (p6) br.cond.sptk 5b
89 (p8) br.cond.spnt 1b;; // Repeat if DEADLOCK occurred.
/arch/arm/net/
Dbpf_jit_32.c113 static inline void _emit(int cond, u32 inst, struct jit_ctx *ctx) in _emit() argument
116 ctx->target[ctx->idx] = inst | (cond << 28); in _emit()
320 static void emit_load_be32(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx) in emit_load_be32() argument
322 _emit(cond, ARM_LDRB_I(ARM_R3, r_addr, 1), ctx); in emit_load_be32()
323 _emit(cond, ARM_LDRB_I(ARM_R1, r_addr, 0), ctx); in emit_load_be32()
324 _emit(cond, ARM_LDRB_I(ARM_R2, r_addr, 3), ctx); in emit_load_be32()
325 _emit(cond, ARM_LSL_I(ARM_R3, ARM_R3, 16), ctx); in emit_load_be32()
326 _emit(cond, ARM_LDRB_I(ARM_R0, r_addr, 2), ctx); in emit_load_be32()
327 _emit(cond, ARM_ORR_S(ARM_R3, ARM_R3, ARM_R1, SRTYPE_LSL, 24), ctx); in emit_load_be32()
328 _emit(cond, ARM_ORR_R(ARM_R3, ARM_R3, ARM_R2), ctx); in emit_load_be32()
[all …]
/arch/ia64/lib/
Dcopy_user.S106 (p10) br.cond.dptk .long_copy_user
156 (p15) br.cond.spnt 1f
166 br.cond.spnt .word_copy_user
203 (p9) br.cond.spnt 4f // if (16 > len1) skip 8-byte copy
235 (pred) br.cond.spnt .copy_user_bit##shift
245 br.cond.sptk.many .diff_align_do_tail; \
254 br.cond.sptk.many .failure_in2
324 (p8) br.cond.dpnt .diff_align_copy_user
365 (p7) br.cond.dpnt .dotail // we have less than 16 bytes left
462 br.cond.dptk.many .failure_in1bis
[all …]
Dmemset.S83 (p_scr) br.cond.dptk.many .move_bytes_unaligned // go move just a few (M_B_U)
119 (p_scr) br.cond.dpnt.many .fraction_of_line // go move just a few
125 (p_zr) br.cond.dptk.many .l1b // Jump to use stf.spill
193 (p_scr) br.cond.dpnt.many .fraction_of_line // Branch no. 2
194 br.cond.dpnt.many .move_bytes_from_alignment // Branch no. 3
247 (p_scr) br.cond.dpnt.many .move_bytes_from_alignment //
258 (p_scr) br.cond.dpnt.many .store_words
277 (p_scr) br.cond.dpnt.many .move_bytes_from_alignment // Branch
299 (p_scr) br.cond.dpnt.few .restore_and_exit
/arch/alpha/boot/
Dmisc.c64 # define Assert(cond,msg) {if(!(cond)) error(msg);} argument
71 # define Assert(cond,msg) argument
/arch/h8300/platform/h8300h/
Dptrace_h8300h.c181 unsigned char cond = h8300_get_reg(task, PT_CCR); in isbranch() local
194 :"=&r"(cond)::"cc"); in isbranch()
195 cond &= condmask[reson >> 1]; in isbranch()
197 return cond == 0; in isbranch()
199 return cond != 0; in isbranch()
/arch/h8300/boot/compressed/
Dmisc.c52 # define Assert(cond,msg) {if(!(cond)) error(msg);} argument
59 # define Assert(cond,msg) argument
/arch/xtensa/include/asm/
Dasmmacro.h64 .macro __loops ar, as, at, incr_log2, mask_log2, cond, ncond
75 loop\cond \at, 99f
/arch/mips/math-emu/
Dcp1emu.c216 unsigned int cond; in cop1Emulate() local
452 cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2]; in cop1Emulate()
454 cond = ctx->fcr31 & FPU_CSR_COND; in cop1Emulate()
460 cond = !cond; in cop1Emulate()
472 if (cond) { in cop1Emulate()
564 cond = fpucondbit[MIPSInst_RT(ir) >> 2]; in cop1Emulate()
565 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) in cop1Emulate()
842 unsigned cond; in fpu_emu() local
891 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; in fpu_emu()
892 if (((ctx->fcr31 & cond) != 0) != in fpu_emu()
[all …]
/arch/ia64/kernel/
Dfsys.S128 (p6) br.cond.spnt.few 1b // yes -> redo the read of tgid and the check
193 (p6) br.cond.spnt.few .fail_einval
242 (p6) br.cond.spnt.few .fail_einval
257 (p6) br.cond.spnt.many fsys_fallback_syscall
319 (p7) br.cond.dpnt.few .time_redo // sequence number changed, redo
336 (p6) br.cond.dpnt.few .time_normalize
438 (p7) br.cond.spnt.many .lock_contention
442 (p7) br.cond.spnt.many .lock_contention
485 (p6) br.cond.dpnt.many .sig_pending
498 (p6) br.cond.spnt.few 1b // yes -> retry
[all …]

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