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Searched refs:config_base (Results 1 – 16 of 16) sorted by relevance

/arch/s390/kernel/
Dperf_cpum_cf.c105 switch (hwc->config_base) { in validate_event()
131 switch (hwc->config_base) { in validate_ctr_version()
157 ctrs_state = cpumf_state_ctl[hwc->config_base]; in validate_ctr_auth()
379 hwc->config_base = get_counter_set(ev); in __hw_perf_event_init()
496 ctr_set_enable(&cpuhw->state, hwc->config_base); in cpumf_pmu_start()
497 ctr_set_start(&cpuhw->state, hwc->config_base); in cpumf_pmu_start()
507 atomic_inc(&cpuhw->ctr_set[hwc->config_base]); in cpumf_pmu_start()
520 if (!atomic_dec_return(&cpuhw->ctr_set[hwc->config_base])) in cpumf_pmu_stop()
521 ctr_set_stop(&cpuhw->state, hwc->config_base); in cpumf_pmu_stop()
544 ctr_set_enable(&cpuhw->state, event->hw.config_base); in cpumf_pmu_add()
[all …]
/arch/x86/kernel/cpu/
Dperf_event_p6.c74 (void)checking_wrmsrl(hwc->config_base, val); in p6_pmu_disable_event()
87 (void)checking_wrmsrl(hwc->config_base, val); in p6_pmu_enable_event()
Dperf_event.h464 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); in __x86_pmu_enable_event()
477 wrmsrl(hwc->config_base, hwc->config); in x86_pmu_disable_event()
Dperf_event_intel.c885 rdmsrl(hwc->config_base, ctrl_val); in intel_pmu_disable_fixed()
887 wrmsrl(hwc->config_base, ctrl_val); in intel_pmu_disable_fixed()
911 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { in intel_pmu_disable_event()
947 rdmsrl(hwc->config_base, ctrl_val); in intel_pmu_enable_fixed()
950 wrmsrl(hwc->config_base, ctrl_val); in intel_pmu_enable_fixed()
977 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { in intel_pmu_enable_event()
Dperf_event_p4.c860 rdmsrl(hwc->config_base, v); in p4_pmu_clear_cccr_ovf()
862 wrmsrl(hwc->config_base, v & ~P4_CCCR_OVF); in p4_pmu_clear_cccr_ovf()
912 (void)checking_wrmsrl(hwc->config_base, in p4_pmu_disable_event()
982 (void)checking_wrmsrl(hwc->config_base, in p4_pmu_enable_event()
Dperf_event.c831 hwc->config_base = 0; in x86_assign_hw_event()
834 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; in x86_assign_hw_event()
837 hwc->config_base = x86_pmu_config_addr(hwc->idx); in x86_assign_hw_event()
/arch/arm/kernel/
Dperf_event_xscale.c298 evt = (hwc->config_base << XSCALE1_COUNT0_EVT_SHFT) | in xscale1pmu_enable_event()
303 evt = (hwc->config_base << XSCALE1_COUNT1_EVT_SHFT) | in xscale1pmu_enable_event()
355 if (XSCALE_PERFCTR_CCNT == event->config_base) { in xscale1pmu_get_event_idx()
641 evtsel |= hwc->config_base << XSCALE2_COUNT0_EVT_SHFT; in xscale2pmu_enable_event()
646 evtsel |= hwc->config_base << XSCALE2_COUNT1_EVT_SHFT; in xscale2pmu_enable_event()
651 evtsel |= hwc->config_base << XSCALE2_COUNT2_EVT_SHFT; in xscale2pmu_enable_event()
656 evtsel |= hwc->config_base << XSCALE2_COUNT3_EVT_SHFT; in xscale2pmu_enable_event()
Dperf_event_v7.c1018 armv7_pmnc_write_evtsel(idx, hwc->config_base); in armv7pmu_enable_event()
1146 unsigned long evtype = event->config_base & ARMV7_EVTYPE_EVENT; in armv7pmu_get_event_idx()
1175 unsigned long config_base = 0; in armv7pmu_set_event_filter() local
1180 config_base |= ARMV7_EXCLUDE_USER; in armv7pmu_set_event_filter()
1182 config_base |= ARMV7_EXCLUDE_PL1; in armv7pmu_set_event_filter()
1184 config_base |= ARMV7_INCLUDE_HYP; in armv7pmu_set_event_filter()
1190 event->config_base = config_base; in armv7pmu_set_event_filter()
Dperf_event_v6.c447 evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT0_SHIFT) | in armv6pmu_enable_event()
451 evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT1_SHIFT) | in armv6pmu_enable_event()
563 if (ARMV6_PERFCTR_CPU_CYCLES == event->config_base) { in armv6pmu_get_event_idx()
Dperf_event.c505 hwc->config_base = 0; in __hw_perf_event_init()
523 hwc->config_base |= (unsigned long)mapping; in __hw_perf_event_init()
/arch/mips/kernel/
Dperf_event_mipsxx.c345 (evt->config_base & M_PERFCTL_CONFIG_MASK) | in mipsxx_pmu_enable_event()
1178 hwc->config_base |= M_TC_EN_ALL; in check_and_calc_range()
1184 hwc->config_base |= M_PERFCTL_VPEID(event->cpu); in check_and_calc_range()
1185 hwc->config_base |= M_TC_EN_VPE; in check_and_calc_range()
1188 hwc->config_base |= M_TC_EN_ALL; in check_and_calc_range()
1230 hwc->config_base = M_PERFCTL_INTERRUPT_ENABLE; in __hw_perf_event_init()
1241 hwc->config_base |= M_PERFCTL_USER; in __hw_perf_event_init()
1243 hwc->config_base |= M_PERFCTL_KERNEL; in __hw_perf_event_init()
1245 hwc->config_base |= M_PERFCTL_EXL; in __hw_perf_event_init()
1248 hwc->config_base |= M_PERFCTL_SUPERVISOR; in __hw_perf_event_init()
[all …]
/arch/powerpc/perf/
Dcore-fsl-emb.c318 write_pmlca(i, event->hw.config_base); in fsl_emb_pmu_add()
517 event->hw.config_base = PMLCA_CE | PMLCA_FCM1 | in fsl_emb_pmu_event_init()
521 event->hw.config_base |= PMLCA_FCU; in fsl_emb_pmu_event_init()
523 event->hw.config_base |= PMLCA_FCS; in fsl_emb_pmu_event_init()
Dcore-book3s.c1141 event->hw.config_base = ev; in power_pmu_event_init()
/arch/alpha/kernel/
Dperf_event.c197 event[0]->hw.config_base = config; in ev67_check_constraints()
200 event[1]->hw.config_base = config; in ev67_check_constraints()
414 cpuc->config = cpuc->event[0]->hw.config_base; in maybe_change_configuration()
657 hwc->config_base = 0; in __hw_perf_event_init()
/arch/sparc/kernel/
Dperf_event.c738 cpuc->pcr = pcr | cpuc->event[0]->hw.config_base; in sparc_pmu_enable()
1149 hwc->config_base = sparc_pmu->irq_bit; in sparc_pmu_event_init()
1151 hwc->config_base |= PCR_UTRACE; in sparc_pmu_event_init()
1153 hwc->config_base |= PCR_STRACE; in sparc_pmu_event_init()
1155 hwc->config_base |= sparc_pmu->hv_bit; in sparc_pmu_event_init()
/arch/mips/include/asm/sn/
Dklconfig.h128 unsigned long config_base; member