| /arch/powerpc/boot/ |
| D | mv64x60_i2c.c | 75 static int mv64x60_i2c_control(int control, int status) in mv64x60_i2c_control() argument
77 out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff); in mv64x60_i2c_control()
81 static int mv64x60_i2c_read_byte(int control, int status) in mv64x60_i2c_read_byte() argument
83 out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff); in mv64x60_i2c_read_byte()
89 static int mv64x60_i2c_write_byte(int data, int control, int status) in mv64x60_i2c_write_byte() argument
92 out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff); in mv64x60_i2c_write_byte()
101 int control; in mv64x60_i2c_read() local
118 control = MV64x60_I2C_CONTROL_START | MV64x60_I2C_CONTROL_TWSIEN; in mv64x60_i2c_read()
120 if (mv64x60_i2c_control(control, status) < 0) in mv64x60_i2c_read()
125 control = MV64x60_I2C_CONTROL_TWSIEN; in mv64x60_i2c_read()
[all …]
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| /arch/arm/mach-rpc/include/mach/ |
| D | acornfb.h | 98 case 1: vidc->control |= VIDC20_CTRL_PIX_CK; break; in acornfb_vidc20_find_rates()
99 case 2: vidc->control |= VIDC20_CTRL_PIX_CK2; break; in acornfb_vidc20_find_rates()
100 case 3: vidc->control |= VIDC20_CTRL_PIX_CK3; break; in acornfb_vidc20_find_rates()
101 case 4: vidc->control |= VIDC20_CTRL_PIX_CK4; break; in acornfb_vidc20_find_rates()
102 case 5: vidc->control |= VIDC20_CTRL_PIX_CK5; break; in acornfb_vidc20_find_rates()
103 case 6: vidc->control |= VIDC20_CTRL_PIX_CK6; break; in acornfb_vidc20_find_rates()
104 case 7: vidc->control |= VIDC20_CTRL_PIX_CK7; break; in acornfb_vidc20_find_rates()
105 case 8: vidc->control |= VIDC20_CTRL_PIX_CK8; break; in acornfb_vidc20_find_rates()
118 vidc->control |= VIDC20_CTRL_FIFO_24; in acornfb_vidc20_find_rates()
120 vidc->control |= VIDC20_CTRL_FIFO_28; in acornfb_vidc20_find_rates()
[all …]
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| /arch/mips/oprofile/ |
| D | op_model_rm9000.c | 32 unsigned int control; member
41 unsigned int control = 0; in rm9000_reg_setup() local
46 control |= RM9K_COUNTER1_EVENT(ctr[0].event) | in rm9000_reg_setup()
51 control |= RM9K_COUNTER2_EVENT(ctr[1].event) | in rm9000_reg_setup()
55 reg.control = control; in rm9000_reg_setup()
74 write_c0_perfcontrol(reg.control); in rm9000_cpu_start()
85 unsigned int control = read_c0_perfcontrol(); in rm9000_perfcount_handler() local
102 if (control & RM9K_COUNTER1_OVERFLOW) { in rm9000_perfcount_handler()
106 if (control & RM9K_COUNTER2_OVERFLOW) { in rm9000_perfcount_handler()
113 write_c0_perfcontrol(reg.control); in rm9000_perfcount_handler()
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| D | op_model_mipsxx.c | 128 unsigned int control[4]; member
141 reg.control[i] = 0; in mipsxx_reg_setup()
147 reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) | in mipsxx_reg_setup()
150 reg.control[i] |= M_PERFCTL_KERNEL; in mipsxx_reg_setup()
152 reg.control[i] |= M_PERFCTL_USER; in mipsxx_reg_setup()
154 reg.control[i] |= M_PERFCTL_EXL; in mipsxx_reg_setup()
188 w_c0_perfctrl3(WHAT | reg.control[3]); in mipsxx_cpu_start()
190 w_c0_perfctrl2(WHAT | reg.control[2]); in mipsxx_cpu_start()
192 w_c0_perfctrl1(WHAT | reg.control[1]); in mipsxx_cpu_start()
194 w_c0_perfctrl0(WHAT | reg.control[0]); in mipsxx_cpu_start()
[all …]
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| /arch/x86/kvm/ |
| D | svm.c | 226 vmcb->control.clean = 0; in mark_all_dirty()
231 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1) in mark_all_clean()
237 vmcb->control.clean &= ~(1 << bit); in mark_dirty()
255 c = &svm->vmcb->control; in recalc_intercepts()
256 h = &svm->nested.hsave->control; in recalc_intercepts()
277 vmcb->control.intercept_cr |= (1U << bit); in set_cr_intercept()
286 vmcb->control.intercept_cr &= ~(1U << bit); in clr_cr_intercept()
295 return vmcb->control.intercept_cr & (1U << bit); in is_cr_intercept()
302 vmcb->control.intercept_dr |= (1U << bit); in set_dr_intercept()
311 vmcb->control.intercept_dr &= ~(1U << bit); in clr_dr_intercept()
[all …]
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| /arch/mips/pci/ |
| D | ops-mace.c | 45 u32 control = mace->pci.control; in mace_pci_read_config() local
48 mace->pci.control = control & ~MACEPCI_CONTROL_MAR_INT; in mace_pci_read_config()
63 mace->pci.control = control; in mace_pci_read_config()
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| D | pci-rc32434.c | 160 rc32434_pci->pcilba[0].control = in rc32434_pcibridge_init()
162 dummyread = rc32434_pci->pcilba[0].control; /* flush the CPU write Buffers */ in rc32434_pcibridge_init()
167 rc32434_pci->pcilba[1].control = in rc32434_pcibridge_init()
169 dummyread = rc32434_pci->pcilba[1].control; /* flush the CPU write Buffers */ in rc32434_pcibridge_init()
174 rc32434_pci->pcilba[2].control = in rc32434_pcibridge_init()
176 dummyread = rc32434_pci->pcilba[2].control; /* flush the CPU write Buffers */ in rc32434_pcibridge_init()
181 rc32434_pci->pcilba[3].control = in rc32434_pcibridge_init()
184 dummyread = rc32434_pci->pcilba[3].control; /* flush the CPU write Buffers */ in rc32434_pcibridge_init()
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| D | msi-octeon.c | 62 u16 control; in arch_setup_msi_irq() local
76 &control); in arch_setup_msi_irq()
84 configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4; in arch_setup_msi_irq()
87 request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1; in arch_setup_msi_irq()
170 control &= ~PCI_MSI_FLAGS_QSIZE; in arch_setup_msi_irq()
171 control |= request_private_bits << 4; in arch_setup_msi_irq()
173 control); in arch_setup_msi_irq()
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| /arch/sparc/kernel/ |
| D | psycho_common.c | 37 u64 control; in psycho_check_stc_error() local
57 control = upa_readq(strbuf->strbuf_control); in psycho_check_stc_error()
58 upa_writeq(control | PSYCHO_STRBUF_CTRL_DENAB, strbuf->strbuf_control); in psycho_check_stc_error()
74 upa_writeq(control, strbuf->strbuf_control); in psycho_check_stc_error()
205 u64 control, iommu_tag[16], iommu_data[16]; in psycho_check_iommu_error() local
210 control = upa_readq(iommu->iommu_control); in psycho_check_iommu_error()
211 if (control & PSYCHO_IOMMU_CTRL_XLTEERR) { in psycho_check_iommu_error()
214 control &= ~PSYCHO_IOMMU_CTRL_XLTEERR; in psycho_check_iommu_error()
215 upa_writeq(control, iommu->iommu_control); in psycho_check_iommu_error()
217 switch ((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) { in psycho_check_iommu_error()
[all …]
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| D | sbus.c | 497 u64 control; in sysio_register_error_handlers() local
532 control = upa_readq(iommu->write_complete_reg); in sysio_register_error_handlers()
533 control |= 0x100UL; /* SBUS Error Interrupt Enable */ in sysio_register_error_handlers()
534 upa_writeq(control, iommu->write_complete_reg); in sysio_register_error_handlers()
546 u64 control; in sbus_iommu_init() local
601 control = upa_readq(iommu->iommu_control); in sbus_iommu_init()
602 control = ((7UL << 16UL) | in sbus_iommu_init()
606 upa_writeq(control, iommu->iommu_control); in sbus_iommu_init()
628 control = (1UL << 1UL) | (1UL << 0UL); in sbus_iommu_init()
629 upa_writeq(control, strbuf->strbuf_control); in sbus_iommu_init()
[all …]
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| D | pci_schizo.c | 132 u64 control; in __schizo_check_stc_error_pbm() local
150 control = upa_readq(strbuf->strbuf_control); in __schizo_check_stc_error_pbm()
151 upa_writeq((control | SCHIZO_STRBUF_CTRL_DENAB), in __schizo_check_stc_error_pbm()
168 upa_writeq(control, strbuf->strbuf_control); in __schizo_check_stc_error_pbm()
241 u64 control; in schizo_check_iommu_error_pbm() local
245 control = upa_readq(iommu->iommu_control); in schizo_check_iommu_error_pbm()
246 if (control & SCHIZO_IOMMU_CTRL_XLTEERR) { in schizo_check_iommu_error_pbm()
251 control &= ~SCHIZO_IOMMU_CTRL_XLTEERR; in schizo_check_iommu_error_pbm()
252 upa_writeq(control, iommu->iommu_control); in schizo_check_iommu_error_pbm()
254 switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) { in schizo_check_iommu_error_pbm()
[all …]
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| /arch/um/drivers/ |
| D | daemon_user.c | 55 pri->control = socket(AF_UNIX, SOCK_STREAM, 0); in connect_to_switch()
56 if (pri->control < 0) { in connect_to_switch()
63 if (connect(pri->control, (struct sockaddr *) ctl_addr, in connect_to_switch()
97 n = write(pri->control, &req, sizeof(req)); in connect_to_switch()
105 n = read(pri->control, sun, sizeof(*sun)); in connect_to_switch()
121 close(pri->control); in connect_to_switch()
166 close(pri->control); in daemon_remove()
167 pri->control = -1; in daemon_remove()
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| D | daemon.h | 20 int control; member
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| /arch/m68k/hp300/ |
| D | hp300map.map | 6 # altgr control keycode 83 = Boot
7 # altgr control keycode 111 = Boot
78 control keycode 63 = nul
90 control keycode 73 = Console_4
92 control keycode 74 = Console_3
94 control keycode 75 = Console_2
96 control keycode 76 = Console_1
102 control keycode 81 = Console_5
104 control keycode 82 = Console_6
106 control keycode 83 = Console_7
[all …]
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| /arch/arm/boot/compressed/ |
| D | big-endian.S | 10 mrc p15, 0, r0, c1, c0, 0 @ read control reg
12 mcr p15, 0, r0, c1, c0, 0 @ write control reg
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| /arch/powerpc/include/asm/ |
| D | dbdma.h | 15 unsigned int control; /* lets you change bits in status */ member
96 out_le32(&((regs)->control), (RUN|FLUSH)<<16); \
102 out_le32(&((regs)->control), (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);\
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| /arch/arm/mm/ |
| D | proc-v6.S | 141 mrc p15, 0, r7, c1, c0, 1 @ auxiliary control register
142 mrc p15, 0, r8, c1, c0, 2 @ co-processor access control
143 mrc p15, 0, r9, c1, c0, 0 @ control register
162 mcr p15, 0, r7, c1, c0, 1 @ auxiliary control register
163 mcr p15, 0, r8, c1, c0, 2 @ co-processor access control
164 mcr p15, 0, ip, c2, c0, 2 @ TTB control register
166 mov r0, r9 @ control register
208 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
220 mrc p15, 0, r0, c1, c0, 0 @ read control register
234 mrceq p15, 0, r5, c1, c0, 1 @ load aux control reg
[all …]
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| D | proc-v7.S | 103 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
105 mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
106 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
127 mcr p15, 0, r11, c2, c0, 2 @ TTB control register
128 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
131 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
138 mov r0, r8 @ control register
193 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
195 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
199 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
[all …]
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| /arch/avr32/mach-at32ap/ |
| D | at32ap700x.c | 115 static unsigned long pll_get_rate(struct clk *clk, unsigned long control) in pll_get_rate() argument
119 div = PM_BFEXT(PLLDIV, control) + 1; in pll_get_rate()
120 mul = PM_BFEXT(PLLMUL, control) + 1; in pll_get_rate()
196 u32 control; in pll0_get_rate() local
198 control = pm_readl(PLL0); in pll0_get_rate()
200 return pll_get_rate(clk, control); in pll0_get_rate()
240 u32 control; in pll1_get_rate() local
242 control = pm_readl(PLL1); in pll1_get_rate()
244 return pll_get_rate(clk, control); in pll1_get_rate()
371 u32 control; in cpu_clk_set_rate() local
[all …]
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| /arch/blackfin/include/asm/ |
| D | bfin_ppi.h | 24 __BFP(control);
43 u32 control; member
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| /arch/mips/pmc-sierra/yosemite/ |
| D | setup.c | 80 m48t37_base->control = 0x40; in read_persistent_clock()
92 m48t37_base->control = 0x00; in read_persistent_clock()
114 m48t37_base->control = 0x80; in rtc_mips_set_time()
135 m48t37_base->control = 0x00; in rtc_mips_set_time()
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| /arch/mips/include/asm/ip32/ |
| D | mace.h | 49 volatile unsigned int control; member
135 volatile unsigned long control; member
140 volatile unsigned long control; /* channel control */ member
240 volatile unsigned long control; member
259 volatile unsigned long control; member
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| /arch/tile/kernel/ |
| D | single_step.c | 730 unsigned long control = __insn_mfspr(SPR_SINGLE_STEP_CONTROL_K); in gx_singlestep_handle() local
736 (!(control & SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK))) { in gx_singlestep_handle()
739 control |= SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK; in gx_singlestep_handle()
740 control |= SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK; in gx_singlestep_handle()
741 __insn_mtspr(SPR_SINGLE_STEP_CONTROL_K, control); in gx_singlestep_handle()
754 unsigned long control = __insn_mfspr(SPR_SINGLE_STEP_CONTROL_K); in single_step_once() local
757 control |= SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK; in single_step_once()
758 control |= SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK; in single_step_once()
759 __insn_mtspr(SPR_SINGLE_STEP_CONTROL_K, control); in single_step_once()
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| /arch/mips/include/asm/mach-cavium-octeon/ |
| D | kernel-entry-init.h | 30 # Read the cavium mem control register
35 dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register
36 dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register
71 # Write the cavium control register
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| /arch/ia64/kernel/ |
| D | palinfo.c | 533 static char * feature_set_info(char *page, u64 avail, u64 status, u64 control, in feature_set_info() argument
541 for(i=0; i < 64; i++, avail >>=1, status >>=1, control >>=1) { in feature_set_info()
543 if (!(control)) /* No remaining bits set */ in feature_set_info()
553 avail & 0x1 ? (control & 0x1 ? in feature_set_info()
561 avail & 0x1 ? (control & 0x1 ? in feature_set_info()
572 u64 avail=1, status=1, control=1, feature_set=0; in processor_info() local
576 ret = ia64_pal_proc_get_features(&avail, &status, &control, in processor_info()
586 p = feature_set_info(p, avail, status, control, feature_set); in processor_info()
626 u64 avail, status, control; in bus_info() local
634 control = ct.pal_bus_features_val; in bus_info()
[all …]
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