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Searched refs:control_reg (Results 1 – 10 of 10) sorted by relevance

/arch/mips/cavium-octeon/executive/
Dcvmx-helper-sgmii.c143 union cvmx_pcsx_mrx_control_reg control_reg; in __cvmx_helper_sgmii_hardware_init_link() local
153 control_reg.u64 = in __cvmx_helper_sgmii_hardware_init_link()
156 control_reg.s.reset = 1; in __cvmx_helper_sgmii_hardware_init_link()
158 control_reg.u64); in __cvmx_helper_sgmii_hardware_init_link()
173 control_reg.s.rst_an = 1; in __cvmx_helper_sgmii_hardware_init_link()
174 control_reg.s.an_en = 1; in __cvmx_helper_sgmii_hardware_init_link()
175 control_reg.s.pwr_dn = 0; in __cvmx_helper_sgmii_hardware_init_link()
177 control_reg.u64); in __cvmx_helper_sgmii_hardware_init_link()
/arch/arm/mach-omap2/
Ddpll44xx.c109 v = __raw_readl(dd->control_reg); in omap4_dpll_regm4xen_recalc()
140 v = __raw_readl(dd->control_reg) & OMAP4430_DPLL_REGM4XEN_MASK; in omap4_dpll_regm4xen_round_rate()
Ddpll3xxx.c54 v = __raw_readl(dd->control_reg); in _omap3_dpll_write_clken()
57 __raw_writel(v, dd->control_reg); in _omap3_dpll_write_clken()
308 v = __raw_readl(dd->control_reg); in omap3_noncore_dpll_program()
311 __raw_writel(v, dd->control_reg); in omap3_noncore_dpll_program()
610 v = __raw_readl(dd->control_reg) & dd->enable_mask; in omap3_clkoutx2_recalc()
Dclkt_dpll.c201 v = __raw_readl(dd->control_reg); in omap2_init_dpll_parent()
248 v = __raw_readl(dd->control_reg); in omap2_get_dpll_rate()
Dclock44xx_data.c256 .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE,
432 .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE,
670 .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA,
738 .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU,
811 .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER,
956 .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB,
Dclock3xxx_data.c283 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
354 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
415 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
572 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
593 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
926 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
Dclock2420_data.c114 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
Dclock2430_data.c113 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
/arch/powerpc/sysdev/qe_lib/
Dqe_ic.c433 u32 temp, control_reg = QEIC_CICNR, shift = 0; in qe_ic_set_high_priority() local
453 control_reg = QEIC_CRICR; in qe_ic_set_high_priority()
457 control_reg = QEIC_CRICR; in qe_ic_set_high_priority()
464 temp = qe_ic_read(qe_ic->regs, control_reg); in qe_ic_set_high_priority()
467 qe_ic_write(qe_ic->regs, control_reg, temp); in qe_ic_set_high_priority()
/arch/arm/plat-omap/include/plat/
Dclock.h150 void __iomem *control_reg; member