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Searched refs:ct (Results 1 – 25 of 49) sorted by relevance

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/arch/powerpc/include/asm/
Dcputime.h49 static inline unsigned long cputime_to_jiffies(const cputime_t ct) in cputime_to_jiffies() argument
51 return mulhdu((__force u64) ct, __cputime_jiffies_factor); in cputime_to_jiffies()
56 static inline cputime_t cputime_to_scaled(const cputime_t ct) in cputime_to_scaled() argument
60 return (__force u64) ct * in cputime_to_scaled()
63 return ct; in cputime_to_scaled()
68 u64 ct; in jiffies_to_cputime() local
72 ct = jif % HZ; in jiffies_to_cputime()
74 if (ct) { in jiffies_to_cputime()
75 ct *= tb_ticks_per_sec; in jiffies_to_cputime()
76 do_div(ct, HZ); in jiffies_to_cputime()
[all …]
/arch/arm/plat-mxc/
Davic.c110 struct irq_chip_type *ct = gc->chip_types; in avic_irq_suspend() local
113 avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask); in avic_irq_suspend()
114 __raw_writel(gc->wake_active, avic_base + ct->regs.mask); in avic_irq_suspend()
120 struct irq_chip_type *ct = gc->chip_types; in avic_irq_resume() local
123 __raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask); in avic_irq_resume()
134 struct irq_chip_type *ct; in avic_init_gc() local
142 ct = gc->chip_types; in avic_init_gc()
143 ct->chip.irq_mask = irq_gc_mask_clr_bit; in avic_init_gc()
144 ct->chip.irq_unmask = irq_gc_mask_set_bit; in avic_init_gc()
145 ct->chip.irq_ack = irq_gc_mask_clr_bit; in avic_init_gc()
[all …]
Dtzic.c108 struct irq_chip_type *ct; in tzic_init_gc() local
116 ct = gc->chip_types; in tzic_init_gc()
117 ct->chip.irq_mask = irq_gc_mask_disable_reg; in tzic_init_gc()
118 ct->chip.irq_unmask = irq_gc_unmask_enable_reg; in tzic_init_gc()
119 ct->chip.irq_set_wake = irq_gc_set_wake; in tzic_init_gc()
120 ct->chip.irq_suspend = tzic_irq_suspend; in tzic_init_gc()
121 ct->chip.irq_resume = tzic_irq_resume; in tzic_init_gc()
122 ct->regs.disable = TZIC_ENCLEAR0(idx); in tzic_init_gc()
123 ct->regs.enable = TZIC_ENSET0(idx); in tzic_init_gc()
/arch/mips/jz4740/
Dirq.c82 struct irq_chip_type *ct; in arch_init_irq() local
96 ct = gc->chip_types; in arch_init_irq()
97 ct->regs.enable = JZ_REG_INTC_CLEAR_MASK; in arch_init_irq()
98 ct->regs.disable = JZ_REG_INTC_SET_MASK; in arch_init_irq()
99 ct->chip.irq_unmask = irq_gc_unmask_enable_reg; in arch_init_irq()
100 ct->chip.irq_mask = irq_gc_mask_disable_reg; in arch_init_irq()
101 ct->chip.irq_mask_ack = irq_gc_mask_disable_reg; in arch_init_irq()
102 ct->chip.irq_set_wake = irq_gc_set_wake; in arch_init_irq()
103 ct->chip.irq_suspend = jz4740_irq_suspend; in arch_init_irq()
104 ct->chip.irq_resume = jz4740_irq_resume; in arch_init_irq()
Dgpio.c422 struct irq_chip_type *ct; in jz4740_gpio_chip_init() local
436 ct = gc->chip_types; in jz4740_gpio_chip_init()
437 ct->regs.enable = JZ_REG_GPIO_MASK_CLEAR; in jz4740_gpio_chip_init()
438 ct->regs.disable = JZ_REG_GPIO_MASK_SET; in jz4740_gpio_chip_init()
439 ct->regs.ack = JZ_REG_GPIO_FLAG_CLEAR; in jz4740_gpio_chip_init()
441 ct->chip.name = "GPIO"; in jz4740_gpio_chip_init()
442 ct->chip.irq_mask = irq_gc_mask_disable_reg; in jz4740_gpio_chip_init()
443 ct->chip.irq_unmask = jz_gpio_irq_unmask; in jz4740_gpio_chip_init()
444 ct->chip.irq_ack = irq_gc_ack_set_bit; in jz4740_gpio_chip_init()
445 ct->chip.irq_suspend = jz4740_irq_suspend; in jz4740_gpio_chip_init()
[all …]
/arch/openrisc/kernel/
Dirq.c123 struct irq_chip_type *ct; in or1k_irq_init() local
129 ct = gc->chip_types; in or1k_irq_init()
131 ct->chip.irq_unmask = or1k_pic_unmask; in or1k_irq_init()
132 ct->chip.irq_mask = or1k_pic_mask; in or1k_irq_init()
133 ct->chip.irq_ack = or1k_pic_ack; in or1k_irq_init()
134 ct->chip.irq_mask_ack = or1k_pic_mask_ack; in or1k_irq_init()
135 ct->chip.irq_set_type = or1k_pic_set_type; in or1k_irq_init()
142 ct->chip.type = IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_MASK; in or1k_irq_init()
/arch/arm/plat-orion/
Dirq.c20 struct irq_chip_type *ct; in orion_irq_init() local
29 ct = gc->chip_types; in orion_irq_init()
30 ct->chip.irq_mask = irq_gc_mask_clr_bit; in orion_irq_init()
31 ct->chip.irq_unmask = irq_gc_mask_set_bit; in orion_irq_init()
Dgpio.c328 struct irq_chip_type *ct = irq_data_get_chip_type(d); in gpio_irq_set_type() local
347 if (!(ct->type & type)) in gpio_irq_set_type()
386 struct irq_chip_type *ct; in orion_gpio_init() local
428 ct = gc->chip_types; in orion_gpio_init()
429 ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF; in orion_gpio_init()
430 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; in orion_gpio_init()
431 ct->chip.irq_mask = irq_gc_mask_clr_bit; in orion_gpio_init()
432 ct->chip.irq_unmask = irq_gc_mask_set_bit; in orion_gpio_init()
433 ct->chip.irq_set_type = gpio_irq_set_type; in orion_gpio_init()
435 ct++; in orion_gpio_init()
[all …]
/arch/arm/mach-davinci/
Dirq.c52 struct irq_chip_type *ct; in davinci_alloc_gc() local
61 ct = gc->chip_types; in davinci_alloc_gc()
62 ct->chip.irq_ack = irq_gc_ack_set_bit; in davinci_alloc_gc()
63 ct->chip.irq_mask = irq_gc_mask_clr_bit; in davinci_alloc_gc()
64 ct->chip.irq_unmask = irq_gc_mask_set_bit; in davinci_alloc_gc()
66 ct->regs.ack = IRQ_REG0_OFFSET; in davinci_alloc_gc()
67 ct->regs.mask = IRQ_ENT_REG0_OFFSET; in davinci_alloc_gc()
/arch/powerpc/mm/
Dicswx.c164 static int acop_use_cop(int ct) in acop_use_cop() argument
200 int ct; in acop_handle_fault() local
215 ct = ICSWX_GET_CT_HINT(error_code); in acop_handle_fault()
216 if (ct < 0) { in acop_handle_fault()
227 ct = (ccw >> 16) & 0x3f; in acop_handle_fault()
243 if ((acop_copro_type_bit(ct) & current->active_mm->context.acop) != 0) { in acop_handle_fault()
249 if (!acop_use_cop(ct)) in acop_handle_fault()
254 current->comm, current->pid, ct); in acop_handle_fault()
/arch/arm/plat-s5p/
Dirq-gpioint.c49 struct irq_chip_type *ct = gc->chip_types; in s5p_gpioint_set_type() local
76 writel(gc->type_cache, gc->reg_base + ct->regs.type); in s5p_gpioint_set_type()
119 struct irq_chip_type *ct; in s5p_gpioint_add() local
161 ct = gc->chip_types; in s5p_gpioint_add()
162 ct->chip.irq_ack = irq_gc_ack_set_bit; in s5p_gpioint_add()
163 ct->chip.irq_mask = irq_gc_mask_set_bit; in s5p_gpioint_add()
164 ct->chip.irq_unmask = irq_gc_mask_clr_bit; in s5p_gpioint_add()
165 ct->chip.irq_set_type = s5p_gpioint_set_type, in s5p_gpioint_add()
166 ct->regs.ack = PEND_OFFSET + REG_OFFSET(group - bank->start); in s5p_gpioint_add()
167 ct->regs.mask = MASK_OFFSET + REG_OFFSET(group - bank->start); in s5p_gpioint_add()
[all …]
/arch/ia64/include/asm/
Dcputime.h72 static inline void cputime_to_timespec(const cputime_t ct, struct timespec *val) in cputime_to_timespec() argument
74 val->tv_sec = (__force u64) ct / NSEC_PER_SEC; in cputime_to_timespec()
75 val->tv_nsec = (__force u64) ct % NSEC_PER_SEC; in cputime_to_timespec()
86 static inline void cputime_to_timeval(const cputime_t ct, struct timeval *val) in cputime_to_timeval() argument
88 val->tv_sec = (__force u64) ct / NSEC_PER_SEC; in cputime_to_timeval()
89 val->tv_usec = ((__force u64) ct % NSEC_PER_SEC) / NSEC_PER_USEC; in cputime_to_timeval()
/arch/arm/plat-samsung/
Dirq-vic-timer.c58 struct irq_chip_type *ct; in s3c_init_vic_timer_irq() local
85 ct = s3c_tgc->chip_types; in s3c_init_vic_timer_irq()
86 ct->chip.irq_mask = irq_gc_mask_clr_bit; in s3c_init_vic_timer_irq()
87 ct->chip.irq_unmask = irq_gc_mask_set_bit; in s3c_init_vic_timer_irq()
88 ct->chip.irq_ack = s3c_irq_timer_ack; in s3c_init_vic_timer_irq()
/arch/arm/mach-prima2/
Dirq.c30 struct irq_chip_type *ct; in sirfsoc_alloc_gc() local
33 ct = gc->chip_types; in sirfsoc_alloc_gc()
35 ct->chip.irq_mask = irq_gc_mask_clr_bit; in sirfsoc_alloc_gc()
36 ct->chip.irq_unmask = irq_gc_mask_set_bit; in sirfsoc_alloc_gc()
37 ct->regs.mask = SIRFSOC_INT_RISC_MASK0; in sirfsoc_alloc_gc()
/arch/x86/lib/
Dstrstr_32.c3 char *strstr(const char *cs, const char *ct) in strstr() argument
27 : "0" (0), "1" (0xffffffff), "2" (cs), "g" (ct) in strstr()
Dstring_32.c94 int strcmp(const char *cs, const char *ct) in strcmp() argument
109 : "1" (cs), "2" (ct) in strcmp()
117 int strncmp(const char *cs, const char *ct, size_t count) in strncmp() argument
134 : "1" (cs), "2" (ct), "3" (count) in strncmp()
/arch/arm/mach-omap2/
Dprm_common.c244 struct irq_chip_type *ct; in omap_prcm_register_chain_handler() local
302 ct = gc->chip_types; in omap_prcm_register_chain_handler()
303 ct->chip.irq_ack = irq_gc_ack_set_bit; in omap_prcm_register_chain_handler()
304 ct->chip.irq_mask = irq_gc_mask_clr_bit; in omap_prcm_register_chain_handler()
305 ct->chip.irq_unmask = irq_gc_mask_set_bit; in omap_prcm_register_chain_handler()
307 ct->regs.ack = irq_setup->ack + i * 4; in omap_prcm_register_chain_handler()
308 ct->regs.mask = irq_setup->mask + i * 4; in omap_prcm_register_chain_handler()
Dirq.c143 struct irq_chip_type *ct; in omap_alloc_gc() local
147 ct = gc->chip_types; in omap_alloc_gc()
148 ct->chip.irq_ack = omap_mask_ack_irq; in omap_alloc_gc()
149 ct->chip.irq_mask = irq_gc_mask_disable_reg; in omap_alloc_gc()
150 ct->chip.irq_unmask = irq_gc_unmask_enable_reg; in omap_alloc_gc()
152 ct->regs.ack = INTC_CONTROL; in omap_alloc_gc()
153 ct->regs.enable = INTC_MIR_CLEAR0; in omap_alloc_gc()
154 ct->regs.disable = INTC_MIR_SET0; in omap_alloc_gc()
/arch/arm/boot/compressed/
Dstring.c68 int memcmp(const void *cs, const void *ct, size_t count) in memcmp() argument
70 const unsigned char *su1 = cs, *su2 = ct, *end = su1 + count; in memcmp()
81 int strcmp(const char *cs, const char *ct) in strcmp() argument
88 c2 = *ct++; in strcmp()
/arch/arm/mach-s5p64x0/
Dcommon.c405 struct irq_chip_type *ct; in s5p64x0_alloc_gc() local
415 ct = gc->chip_types; in s5p64x0_alloc_gc()
416 ct->chip.irq_ack = irq_gc_ack_set_bit; in s5p64x0_alloc_gc()
417 ct->chip.irq_mask = irq_gc_mask_set_bit; in s5p64x0_alloc_gc()
418 ct->chip.irq_unmask = irq_gc_mask_clr_bit; in s5p64x0_alloc_gc()
419 ct->chip.irq_set_type = s5p64x0_irq_eint_set_type; in s5p64x0_alloc_gc()
420 ct->chip.irq_set_wake = s3c_irqext_wake; in s5p64x0_alloc_gc()
421 ct->regs.ack = EINT0PEND_OFFSET; in s5p64x0_alloc_gc()
422 ct->regs.mask = EINT0MASK_OFFSET; in s5p64x0_alloc_gc()
/arch/blackfin/include/asm/
Dstring.h21 extern int strcmp(const char *cs, const char *ct);
24 extern int strncmp(const char *cs, const char *ct, size_t count);
/arch/x86/kernel/cpu/
Dcentaur.c101 int ct = 0; in centaur_mcr_compute() local
103 while (ct < nr) { in centaur_mcr_compute()
141 centaur_mcr_insert(ct, floor, fspace, key); in centaur_mcr_compute()
144 centaur_mcr_insert(ct, top, high, key); in centaur_mcr_compute()
148 centaur_mcr_insert(ct, base, low, key); in centaur_mcr_compute()
151 ct++; in centaur_mcr_compute()
157 return ct; in centaur_mcr_compute()
/arch/x86/include/asm/
Dstring_64.h60 int memcmp(const void *cs, const void *ct, size_t count);
64 int strcmp(const char *cs, const char *ct);
/arch/s390/lib/
Dstring.c212 int strcmp(const char *cs, const char *ct) in strcmp() argument
224 : "+d" (ret), "+d" (r0), "+a" (cs), "+a" (ct) in strcmp()
312 int memcmp(const void *cs, const void *ct, size_t n) in memcmp() argument
316 register unsigned long r4 asm("4") = (unsigned long) ct; in memcmp()
/arch/arm/mach-vexpress/
DMakefile6 obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o

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