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Searched refs:ctl (Results 1 – 25 of 45) sorted by relevance

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/arch/alpha/oprofile/
Dop_model_ev5.c31 int i, ctl, reset, need_reset; in common_reg_setup() local
46 ctl = 0; in common_reg_setup()
62 ctl |= event << 31; in common_reg_setup()
66 ctl |= (event - 24) << 4; in common_reg_setup()
68 ctl |= (event - 40) << cbox1_ofs | 15 << 4; in common_reg_setup()
70 ctl |= event - 48; in common_reg_setup()
72 ctl |= (event - 64) << cbox2_ofs | 15; in common_reg_setup()
74 reg->mux_select = ctl; in common_reg_setup()
79 ctl = 0; in common_reg_setup()
80 ctl |= !sys->enable_pal << 9; in common_reg_setup()
[all …]
Dop_model_ev4.c25 unsigned long ctl = 0, count, hilo; in ev4_reg_setup() local
40 ctl |= (ctr[0].enabled ? ctr[0].event << 8 : 14 << 8); in ev4_reg_setup()
41 ctl |= (ctr[1].enabled ? (ctr[1].event - 16) << 32 : 7ul << 32); in ev4_reg_setup()
55 ctl |= (ctr[0].enabled && hilo) << 3; in ev4_reg_setup()
63 ctl |= (ctr[1].enabled && hilo); in ev4_reg_setup()
65 reg->mux_select = ctl; in ev4_reg_setup()
Dop_model_ev6.c25 unsigned long ctl, reset, need_reset, i; in ev6_reg_setup() local
29 ctl = 0; in ev6_reg_setup()
31 ctl |= (ctr[0].event & 1) << 4; in ev6_reg_setup()
33 ctl |= (ctr[1].event - 2) & 15; in ev6_reg_setup()
34 reg->mux_select = ctl; in ev6_reg_setup()
Dop_model_ev67.c26 unsigned long ctl, reset, need_reset, i; in ev67_reg_setup() local
29 ctl = 1UL << 4; /* Enable ProfileMe mode. */ in ev67_reg_setup()
34 ctl |= (ctr[1].event & 3) << 2; in ev67_reg_setup()
37 ctl |= 1UL << 2; in ev67_reg_setup()
39 reg->mux_select = ctl; in ev67_reg_setup()
/arch/x86/include/asm/
Dgart.h63 u32 ctl; in gart_set_size_and_enable() local
69 ctl = order << 1; in gart_set_size_and_enable()
71 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl); in gart_set_size_and_enable()
76 u32 tmp, ctl; in enable_gart_translation() local
85 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl); in enable_gart_translation()
86 ctl |= GARTEN | DISTLBWALKPRB; in enable_gart_translation()
87 ctl &= ~(DISGARTCPU | DISGARTIO); in enable_gart_translation()
88 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl); in enable_gart_translation()
/arch/x86/kernel/
Dvsmp_64.c86 unsigned int cap, ctl, cfg; in set_vsmp_pv_ops() local
92 ctl = readl(address + 4); in set_vsmp_pv_ops()
94 cap, ctl); in set_vsmp_pv_ops()
95 if (cap & ctl & (1 << 4)) { in set_vsmp_pv_ops()
103 ctl &= ~(1 << 4); in set_vsmp_pv_ops()
104 writel(ctl, address + 4); in set_vsmp_pv_ops()
105 ctl = readl(address + 4); in set_vsmp_pv_ops()
106 printk(KERN_INFO "vSMP CTL: control set to:0x%08x\n", ctl); in set_vsmp_pv_ops()
Daperture_64.c276 u32 ctl; in early_gart_iommu_check() local
300 ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL); in early_gart_iommu_check()
301 aper_enabled = ctl & GARTEN; in early_gart_iommu_check()
302 aper_order = (ctl >> 1) & 7; in early_gart_iommu_check()
355 ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL); in early_gart_iommu_check()
356 ctl &= ~GARTEN; in early_gart_iommu_check()
357 write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl); in early_gart_iommu_check()
387 u32 ctl; in gart_iommu_hole_init() local
401 ctl = read_pci_config(bus, slot, 3, in gart_iommu_hole_init()
410 ctl &= ~GARTEN; in gart_iommu_hole_init()
[all …]
/arch/frv/kernel/
Dpm.c153 static int sysctl_pm_do_suspend(ctl_table *ctl, int write, in sysctl_pm_do_suspend() argument
201 static int cmode_procctl(ctl_table *ctl, int write, in cmode_procctl() argument
207 return proc_dointvec(ctl, write, buffer, lenp, fpos); in cmode_procctl()
273 static int p0_procctl(ctl_table *ctl, int write, in p0_procctl() argument
279 return proc_dointvec(ctl, write, buffer, lenp, fpos); in p0_procctl()
286 static int cm_procctl(ctl_table *ctl, int write, in cm_procctl() argument
292 return proc_dointvec(ctl, write, buffer, lenp, fpos); in cm_procctl()
/arch/alpha/kernel/
Dsys_marvel.c74 volatile unsigned long *ctl; in io7_get_irq_ctl() local
97 ctl = &io7->csrs->PO7_LSI_CTL[irq & 0xff].csr; /* assume LSI */ in io7_get_irq_ctl()
99 ctl = &io7->csrs->PO7_MSI_CTL[((irq - 0x80) >> 5) & 0x0f].csr; in io7_get_irq_ctl()
102 return ctl; in io7_get_irq_ctl()
108 volatile unsigned long *ctl; in io7_enable_irq() local
112 ctl = io7_get_irq_ctl(irq, &io7); in io7_enable_irq()
113 if (!ctl || !io7) { in io7_enable_irq()
120 *ctl |= 1UL << 24; in io7_enable_irq()
122 *ctl; in io7_enable_irq()
129 volatile unsigned long *ctl; in io7_disable_irq() local
[all …]
/arch/c6x/platforms/
Ddscr.c96 struct devstate_ctl_reg *ctl; member
192 struct devstate_ctl_reg *ctl; in dscr_set_devstate() local
206 ctl = info->ctl; in dscr_set_devstate()
209 if (ctl == NULL) in dscr_set_devstate()
212 ctl_shift = ctl->shift + ctl->nbits * (id - ctl->start_id); in dscr_set_devstate()
213 ctl_mask = ((1 << ctl->nbits) - 1) << ctl_shift; in dscr_set_devstate()
217 ctl_val = ctl->enable << ctl_shift; in dscr_set_devstate()
220 if (ctl->enable_only) in dscr_set_devstate()
222 ctl_val = ctl->disable << ctl_shift; in dscr_set_devstate()
230 val = soc_readl(dscr.base + ctl->reg); in dscr_set_devstate()
[all …]
/arch/arm/mach-bcmring/csp/dmac/
DdmacHw_extra.c281 (*fpPrint) ("ctl.lo 0x%0X\n", pStart->ctl.lo); in DisplayDescRing()
282 (*fpPrint) ("ctl.hi 0x%0X\n", pStart->ctl.hi); in DisplayDescRing()
308 (*fpPrint) ("ctl.lo 0x%0X\n", pStart->ctl.lo); in DisplayDescRing()
309 (*fpPrint) ("ctl.hi 0x%0X\n", pStart->ctl.hi); in DisplayDescRing()
329 (dmacHw_GET_DESC_RING(pDescriptor))->pTail->ctl. in DmaIsFlowController()
371 pProg->ctl.hi = srcTs & dmacHw_REG_CTL_BLOCK_TS_MASK; in dmacHw_setDataLength()
642 && (pRing->pFree->ctl.lo & dmacHw_DESC_FREE)) { in dmacHw_freeMem()
719 if (((pRing->pHead->ctl.hi & dmacHw_DESC_FREE) == 0) || in dmacHw_setVariableDataDescriptor()
742 pRing->pHead->ctl.lo = controlParam; in dmacHw_setVariableDataDescriptor()
746 pRing->pHead->ctl.hi = 0; in dmacHw_setVariableDataDescriptor()
[all …]
DdmacHw.c135 if (!(pProg->ctl.hi & dmacHw_REG_CTL_DONE)) { in dmacHw_initiateTransfer()
142 pProg->ctl.lo; in dmacHw_initiateTransfer()
145 pProg->ctl.hi; in dmacHw_initiateTransfer()
178 pRing->pProg->ctl.lo |= in dmacHw_initiateTransfer()
187 pRing->pProg->ctl.lo |= in dmacHw_initiateTransfer()
202 pProg->ctl.lo; in dmacHw_initiateTransfer()
204 pProg->ctl.hi; in dmacHw_initiateTransfer()
421 pDesc->ctl.hi = dmacHw_DESC_FREE; in dmacHw_initDescriptor()
436 pDesc->ctl.hi = dmacHw_DESC_FREE; in dmacHw_initDescriptor()
678 if ((pProg->ctl.hi & dmacHw_DESC_FREE) == 0) { in dmacHw_setDataDescriptor()
[all …]
/arch/powerpc/sysdev/
Dfsl_85xx_l2ctlr.c138 clrsetbits_be32(&l2ctlr->ctl, L2CR_L2E, L2CR_L2FI); in mpc85xx_l2ctlr_of_probe()
142 setbits32(&l2ctlr->ctl, in mpc85xx_l2ctlr_of_probe()
147 setbits32(&l2ctlr->ctl, in mpc85xx_l2ctlr_of_probe()
152 setbits32(&l2ctlr->ctl, in mpc85xx_l2ctlr_of_probe()
158 setbits32(&l2ctlr->ctl, in mpc85xx_l2ctlr_of_probe()
Dfsl_85xx_cache_ctlr.h51 u32 ctl; /* 0x000 - L2 control */ member
/arch/x86/oprofile/
Dop_model_amd.c136 u64 val, ctl; in op_amd_handle_ibs() local
143 rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl); in op_amd_handle_ibs()
144 if (ctl & IBS_FETCH_VAL) { in op_amd_handle_ibs()
149 oprofile_add_data64(&entry, ctl); in op_amd_handle_ibs()
155 ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT); in op_amd_handle_ibs()
156 ctl |= IBS_FETCH_ENABLE; in op_amd_handle_ibs()
157 wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl); in op_amd_handle_ibs()
162 rdmsrl(MSR_AMD64_IBSOPCTL, ctl); in op_amd_handle_ibs()
163 if (ctl & IBS_OP_VAL) { in op_amd_handle_ibs()
185 ctl = op_amd_randomize_ibs_op(ibs_state.ibs_op_ctl); in op_amd_handle_ibs()
[all …]
/arch/powerpc/platforms/85xx/
Dxes_mpc85xx.c53 volatile uint32_t ctl, tmp; in xes_mpc85xx_configure_l2() local
64 ctl = MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2I; in xes_mpc85xx_configure_l2()
71 ctl |= (tmp & MPC85xx_L2CTL_L2SIZ_MASK) >> 2; in xes_mpc85xx_configure_l2()
74 out_be32(l2_base, ctl); in xes_mpc85xx_configure_l2()
/arch/s390/include/asm/
Dcpu_mf.h69 static inline int lcctl(u64 ctl) in lcctl() argument
77 : "=d" (cc) : "m" (ctl) : "cc"); in lcctl()
/arch/s390/appldata/
Dappldata_base.c53 static int appldata_timer_handler(ctl_table *ctl, int write,
55 static int appldata_interval_handler(ctl_table *ctl, int write,
247 appldata_timer_handler(ctl_table *ctl, int write, in appldata_timer_handler() argument
289 appldata_interval_handler(ctl_table *ctl, int write, in appldata_interval_handler() argument
335 appldata_generic_handler(ctl_table *ctl, int write, in appldata_generic_handler() argument
347 if (&tmp_ops->ctl_table[2] == ctl) { in appldata_generic_handler()
355 ops = ctl->data; in appldata_generic_handler()
/arch/x86/kernel/cpu/mcheck/
Dmce-internal.h18 u64 ctl; /* subevents to enable */ member
/arch/mips/include/asm/mach-lantiq/xway/
Dxway_dma.h33 u32 ctl; member
/arch/blackfin/include/asm/
Dbfin5xx_spi.h54 __BFP(ctl);
/arch/mips/include/asm/mach-rc32434/
Drb.h64 u32 ctl; member
/arch/s390/mm/
Dcmm.c256 static int cmm_pages_handler(ctl_table *ctl, int write, void __user *buffer, in cmm_pages_handler() argument
276 if (ctl == &cmm_table[0]) in cmm_pages_handler()
281 if (ctl == &cmm_table[0]) in cmm_pages_handler()
296 static int cmm_timeout_handler(ctl_table *ctl, int write, void __user *buffer, in cmm_timeout_handler() argument
/arch/sparc/include/asm/
Dsbi.h15 /* 0x0004 */ u32 ctl; /* Control */ member
/arch/arm/mach-bcmring/include/mach/csp/
DdmacHw_priv.h37 dmacHw_REG64_t ctl; /* Control Register. 64 bits */ member

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