| /arch/c6x/platforms/ |
| D | dscr.c | 117 static struct dscr_regs dscr; variable
124 if (dscr.locked[i].key && reg == dscr.locked[i].reg) in find_locked_reg()
125 return &dscr.locked[i]; in find_locked_reg()
135 void __iomem *reg_addr = dscr.base + reg; in dscr_write_locked1()
136 void __iomem *lock_addr = dscr.base + lock; in dscr_write_locked1()
165 soc_writel(key0, dscr.base + lock0); in dscr_write_locked2()
166 soc_writel(key1, dscr.base + lock1); in dscr_write_locked2()
167 soc_writel(val, dscr.base + reg); in dscr_write_locked2()
168 soc_writel(0, dscr.base + lock0); in dscr_write_locked2()
169 soc_writel(0, dscr.base + lock1); in dscr_write_locked2()
[all …]
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| D | Makefile | 8 obj-y += dscr.o
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| /arch/c6x/boot/dts/ |
| D | tms320c6455.dtsi | 56 ti,dscr-dev-enable = <13>;
67 ti,dscr-dev-enable = <4>;
79 compatible = "ti,c64x+dscr";
82 ti,dscr-devstat = <0>;
83 ti,dscr-silicon-rev = <8 28 0xf>;
84 ti,dscr-rmii-resets = <0 0x40020 0x00040000>;
86 ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>;
87 ti,dscr-devstate-ctl-regs =
91 ti,dscr-devstate-stat-regs =
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| D | tms320c6472.dtsi | 113 compatible = "ti,c64x+dscr";
116 ti,dscr-devstat = <0>;
117 ti,dscr-silicon-rev = <0x70c 16 0xff>;
119 ti,dscr-mac-fuse-regs = <0x700 1 2 3 4
122 ti,dscr-rmii-resets = <0x208 1
125 ti,dscr-locked-regs = <0x200 0x204 0x0a1e183a
129 ti,dscr-privperm = <0x41c 0xaaaaaaaa>;
131 ti,dscr-devstate-ctl-regs = <0 13 0x200 1 0 0 1>;
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| D | tms320c6457.dtsi | 44 compatible = "ti,c64x+dscr";
47 ti,dscr-devstat = <0x20>;
48 ti,dscr-silicon-rev = <0x18 28 0xf>;
49 ti,dscr-mac-fuse-regs = <0x114 3 4 5 6
51 ti,dscr-kick-regs = <0x38 0x83E70B13
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| D | tms320c6474.dtsi | 72 compatible = "ti,c64x+dscr";
75 ti,dscr-devstat = <0x004>;
76 ti,dscr-silicon-rev = <0x014 28 0xf>;
77 ti,dscr-mac-fuse-regs = <0x34 3 4 5 6
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| /arch/arm/kernel/ |
| D | hw_breakpoint.c | 233 u32 dscr; in enable_monitor_mode() local
236 ARM_DBG_READ(c1, 0, dscr); in enable_monitor_mode()
239 if (WARN_ONCE(dscr & ARM_DSCR_HDBGEN, in enable_monitor_mode()
246 if (dscr & ARM_DSCR_MDBGEN) in enable_monitor_mode()
253 ARM_DBG_WRITE(c1, 0, (dscr | ARM_DSCR_MDBGEN)); in enable_monitor_mode()
257 ARM_DBG_WRITE(c2, 2, (dscr | ARM_DSCR_MDBGEN)); in enable_monitor_mode()
265 ARM_DBG_READ(c1, 0, dscr); in enable_monitor_mode()
266 if (!(dscr & ARM_DSCR_MDBGEN)) in enable_monitor_mode()
852 u32 dscr; in hw_breakpoint_pending() local
860 ARM_DBG_READ(c1, 0, dscr); in hw_breakpoint_pending()
[all …]
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| /arch/mips/alchemy/common/ |
| D | dbdma.c | 934 u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr) in au1xxx_dbdma_put_dscr() argument
961 dp->dscr_dest0 = dscr->dscr_dest0; in au1xxx_dbdma_put_dscr()
962 dp->dscr_source0 = dscr->dscr_source0; in au1xxx_dbdma_put_dscr()
963 dp->dscr_dest1 = dscr->dscr_dest1; in au1xxx_dbdma_put_dscr()
964 dp->dscr_source1 = dscr->dscr_source1; in au1xxx_dbdma_put_dscr()
965 dp->dscr_cmd1 = dscr->dscr_cmd1; in au1xxx_dbdma_put_dscr()
966 nbytes = dscr->dscr_cmd1; in au1xxx_dbdma_put_dscr()
969 dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V; in au1xxx_dbdma_put_dscr()
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| /arch/powerpc/kernel/ |
| D | sysfs.c | 179 SYSFS_PMCSETUP(dscr, SPRN_DSCR);
184 static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
200 current->thread.dscr = dscr_default; in update_dscr()
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| D | process.c | 803 p->thread.dscr = current->thread.dscr; in copy_thread()
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| D | asm-offsets.c | 78 DEFINE(THREAD_DSCR, offsetof(struct thread_struct, dscr)); in main()
454 DEFINE(VCPU_DSCR, offsetof(struct kvm_vcpu, arch.dscr)); in main()
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| D | traps.c | 981 current->thread.dscr = regs->gpr[rd]; in emulate_instruction()
983 mtspr(SPRN_DSCR, current->thread.dscr); in emulate_instruction()
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| /arch/mips/include/asm/mach-au1x00/ |
| D | au1xxx_dbdma.h | 375 u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr);
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| /arch/powerpc/include/asm/ |
| D | processor.h | 247 unsigned long dscr; member
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| D | kvm_host.h | 365 ulong dscr; member
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