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/arch/mips/powertv/asic/
Dprealloc-gaia.c38 .end = 0x241FFFFF, /* 2MiB */
44 .end = 0x24201FFF,
50 .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
61 .end = 0x601FFFFF, /* 2MiB */
67 .end = 0x60201FFF,
73 .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
92 .end = 0x000FFFFF,
98 .end = 0x00009FFF,
104 .end = 0x00003FFF,
110 .end = 0x00003FFF,
[all …]
Dprealloc.h31 .end = (END), \
44 #define PREALLOC_NORMAL(name, start, end, flags) \ argument
45 PREALLOC(name, start, end, flags)
47 #define PREALLOC_NORMAL(name, start, end, flags) argument
51 #define PREALLOC_TFTP(name, start, end, flags) \ argument
52 PREALLOC(name, start, end, flags)
54 #define PREALLOC_TFTP(name, start, end, flags) argument
58 #define PREALLOC_DOCSIS(name, start, end, flags) \ argument
59 PREALLOC(name, start, end, flags)
61 #define PREALLOC_DOCSIS(name, start, end, flags) argument
[all …]
/arch/arm/mach-exynos/
Ddev-sysmmu.c45 .end = EXYNOS4_PA_SYSMMU_MDMA + SZ_64K - 1,
50 .end = IRQ_SYSMMU_MDMA0_0,
55 .end = EXYNOS4_PA_SYSMMU_SSS + SZ_64K - 1,
60 .end = IRQ_SYSMMU_SSS_0,
65 .end = EXYNOS4_PA_SYSMMU_FIMC0 + SZ_64K - 1,
70 .end = IRQ_SYSMMU_FIMC0_0,
75 .end = EXYNOS4_PA_SYSMMU_FIMC1 + SZ_64K - 1,
80 .end = IRQ_SYSMMU_FIMC1_0,
85 .end = EXYNOS4_PA_SYSMMU_FIMC2 + SZ_64K - 1,
90 .end = IRQ_SYSMMU_FIMC2_0,
[all …]
Ddev-audio.c67 .end = EXYNOS4_PA_I2S0 + 0x100 - 1,
72 .end = DMACH_I2S0_TX,
77 .end = DMACH_I2S0_RX,
82 .end = DMACH_I2S0S_TX,
115 .end = EXYNOS4_PA_I2S1 + 0x100 - 1,
120 .end = DMACH_I2S1_TX,
125 .end = DMACH_I2S1_RX,
143 .end = EXYNOS4_PA_I2S2 + 0x100 - 1,
148 .end = DMACH_I2S2_TX,
153 .end = DMACH_I2S2_RX,
[all …]
/arch/blackfin/include/asm/
Dcacheflush.h28 #define flush_cache_range(vma, start, end) do { } while (0) argument
30 #define flush_cache_vmap(start, end) do { } while (0) argument
31 #define flush_cache_vunmap(start, end) do { } while (0) argument
34 #define flush_icache_range_others(start, end) \ argument
35 smp_icache_flush_range_others((start), (end))
37 #define flush_icache_range_others(start, end) do { } while (0) argument
40 static inline void flush_icache_range(unsigned start, unsigned end) in flush_icache_range() argument
43 if (end <= physical_mem_end) in flush_icache_range()
44 blackfin_dcache_flush_range(start, end); in flush_icache_range()
47 if (start >= L2_START && end <= L2_START + L2_LENGTH) in flush_icache_range()
[all …]
/arch/mips/mti-malta/
Dmalta-pci.c43 .end = 0x000fffffUL,
93 resource_size_t start, end, map, start1, end1, map1, map2, map3, mask; in mips_pcibios_init() local
116 end = GT_READ(GT_PCI0M0HD_OFS); in mips_pcibios_init()
118 end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK); in mips_pcibios_init()
124 if (end1 - start1 > end - start) { in mips_pcibios_init()
126 end = end1; in mips_pcibios_init()
129 mask = ~(start ^ end); in mips_pcibios_init()
134 gt64120_mem_resource.end = end; in mips_pcibios_init()
138 gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF; in mips_pcibios_init()
139 gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1; in mips_pcibios_init()
[all …]
/arch/arm/mach-pxa/
Ddevices.c39 .end = IRQ_PMU,
53 .end = 0x41100fff,
58 .end = IRQ_MMC,
63 .end = 21,
68 .end = 22,
104 .end = 0x4060ffff,
109 .end = IRQ_USB,
142 .end = 0x54100fff,
147 .end = IRQ_USB2,
168 .end = 0x4400ffff,
[all …]
/arch/mn10300/include/asm/
Dcacheflush.h25 extern void mn10300_local_icache_inv_range(unsigned long start, unsigned long end);
29 extern void mn10300_local_dcache_inv_range(unsigned long start, unsigned long end);
33 extern void mn10300_icache_inv_range(unsigned long start, unsigned long end);
37 extern void mn10300_dcache_inv_range(unsigned long start, unsigned long end);
42 extern void mn10300_local_dcache_flush_range(unsigned long start, unsigned long end);
46 extern void mn10300_local_dcache_flush_inv_range(unsigned long start, unsigned long end);
50 extern void mn10300_dcache_flush_range(unsigned long start, unsigned long end);
54 extern void mn10300_dcache_flush_inv_range(unsigned long start, unsigned long end);
59 #define mn10300_local_dcache_flush_range(start, end) do {} while (0) argument
65 #define mn10300_local_dcache_flush_inv_range(start, end) \ argument
[all …]
/arch/arm/mach-tegra/
Ddevices.c38 .end = TEGRA_GPIO_BASE + TEGRA_GPIO_SIZE-1,
43 .end = INT_GPIO1,
48 .end = INT_GPIO2,
53 .end = INT_GPIO3,
58 .end = INT_GPIO4,
63 .end = INT_GPIO5,
68 .end = INT_GPIO6,
73 .end = INT_GPIO7,
89 .end = TEGRA_APB_MISC_BASE + 0x20 + 3,
95 .end = TEGRA_APB_MISC_BASE + 0x9c + 3,
[all …]
/arch/s390/lib/
Ddelay.c33 u64 clock_saved, end; in __udelay_disabled() local
35 end = get_clock() + (usecs << 12); in __udelay_disabled()
45 set_clock_comparator(end); in __udelay_disabled()
48 } while (get_clock() < end); in __udelay_disabled()
57 u64 clock_saved, end; in __udelay_enabled() local
59 end = get_clock() + (usecs << 12); in __udelay_enabled()
62 if (end < S390_lowcore.clock_comparator) { in __udelay_enabled()
64 set_clock_comparator(end); in __udelay_enabled()
70 } while (get_clock() < end); in __udelay_enabled()
112 u64 end; in udelay_simple() local
[all …]
/arch/arm/mm/
Dcache-feroceon-l2.c68 static inline void l2_clean_pa_range(unsigned long start, unsigned long end) in l2_clean_pa_range() argument
77 BUG_ON((start ^ end) >> PAGE_SHIFT); in l2_clean_pa_range()
80 va_end = va_start + (end - start); in l2_clean_pa_range()
99 static inline void l2_inv_pa_range(unsigned long start, unsigned long end) in l2_inv_pa_range() argument
108 BUG_ON((start ^ end) >> PAGE_SHIFT); in l2_inv_pa_range()
111 va_end = va_start + (end - start); in l2_inv_pa_range()
137 static unsigned long calc_range_end(unsigned long start, unsigned long end) in calc_range_end() argument
142 BUG_ON(end & (CACHE_LINE_SIZE - 1)); in calc_range_end()
147 range_end = end; in calc_range_end()
166 static void feroceon_l2_inv_range(unsigned long start, unsigned long end) in feroceon_l2_inv_range() argument
[all …]
/arch/c6x/include/asm/
Dcache.h59 extern void enable_caching(unsigned long start, unsigned long end);
60 extern void disable_caching(unsigned long start, unsigned long end);
73 extern void L1P_cache_block_invalidate(unsigned int start, unsigned int end);
74 extern void L1D_cache_block_invalidate(unsigned int start, unsigned int end);
76 unsigned int end);
77 extern void L1D_cache_block_writeback(unsigned int start, unsigned int end);
78 extern void L2_cache_block_invalidate(unsigned int start, unsigned int end);
79 extern void L2_cache_block_writeback(unsigned int start, unsigned int end);
81 unsigned int end);
83 unsigned int end);
[all …]
/arch/microblaze/kernel/cpu/
Dcache.c104 #define CACHE_LOOP_LIMITS(start, end, cache_line_length, cache_size) \ argument
107 end = min(start + cache_size, end); \
136 #define CACHE_RANGE_LOOP_2(start, end, line_length, op) \ argument
141 end = ((end & align) == end) ? end - line_length : end & align; \
142 count = end - start; \
153 #define CACHE_RANGE_LOOP_1(start, end, line_length, op) \ argument
157 end = ((end & align) == end) ? end - line_length : end & align; \
158 WARN_ON(end - start < 0); \
164 " : : "r" (temp), "r" (start), "r" (end),\
170 static void __flush_icache_range_msr_irq(unsigned long start, unsigned long end) in __flush_icache_range_msr_irq() argument
[all …]
/arch/mn10300/mm/
Dcache-inv-icache.c28 static void flush_icache_page_range(unsigned long start, unsigned long end) in flush_icache_page_range() argument
39 size = end - start; in flush_icache_page_range()
72 smp_cache_call(SMP_ICACHE_INV_RANGE, start, end); in flush_icache_page_range()
84 void flush_icache_range(unsigned long start, unsigned long end) in flush_icache_range() argument
91 if (end > 0x80000000UL) { in flush_icache_range()
93 if (end > 0xa0000000UL) { in flush_icache_range()
94 end = 0xa0000000UL; in flush_icache_range()
95 if (start >= end) in flush_icache_range()
103 mn10300_icache_inv_range(start_page, end); in flush_icache_range()
104 smp_cache_call(SMP_ICACHE_INV_RANGE, start, end); in flush_icache_range()
[all …]
Dcache-flush-icache.c50 static void flush_icache_page_range(unsigned long start, unsigned long end) in flush_icache_page_range() argument
61 size = end - start; in flush_icache_page_range()
96 smp_cache_call(SMP_IDCACHE_INV_FLUSH_RANGE, start, end); in flush_icache_page_range()
108 void flush_icache_range(unsigned long start, unsigned long end) in flush_icache_range() argument
115 if (end > 0x80000000UL) { in flush_icache_range()
117 if (end > 0xa0000000UL) { in flush_icache_range()
118 end = 0xa0000000UL; in flush_icache_range()
119 if (start >= end) in flush_icache_range()
127 mn10300_local_dcache_flush_range(start_page, end); in flush_icache_range()
128 mn10300_local_icache_inv_range(start_page, end); in flush_icache_range()
[all …]
/arch/x86/kernel/
Dcheck.c30 char *end; in set_corruption_check() local
32 memory_corruption_check = simple_strtol(arg, &end, 10); in set_corruption_check()
34 return (*end == 0) ? 0 : -EINVAL; in set_corruption_check()
40 char *end; in set_corruption_check_period() local
42 corruption_check_period = simple_strtoul(arg, &end, 10); in set_corruption_check_period()
44 return (*end == 0) ? 0 : -EINVAL; in set_corruption_check_period()
50 char *end; in set_corruption_check_size() local
53 size = memparse(arg, &end); in set_corruption_check_size()
55 if (*end == '\0') in set_corruption_check_size()
65 phys_addr_t start, end; in setup_bios_corruption_check() local
[all …]
/arch/xtensa/mm/
Dinit.c50 int __init mem_reserve(unsigned long start, unsigned long end, int must_exist) in mem_reserve() argument
54 if (start == end) in mem_reserve()
58 end = PAGE_ALIGN(end); in mem_reserve()
61 if (start < sysmem.bank[i].end in mem_reserve()
62 && end >= sysmem.bank[i].start) in mem_reserve()
68 "not in any region!\n", start, end); in mem_reserve()
73 if (end < sysmem.bank[i].end) { in mem_reserve()
77 sysmem.bank[sysmem.nr_banks].start = end; in mem_reserve()
78 sysmem.bank[sysmem.nr_banks].end = sysmem.bank[i].end; in mem_reserve()
81 sysmem.bank[i].end = start; in mem_reserve()
[all …]
/arch/blackfin/mach-bf548/boards/
Dcm_bf548.c56 .end = IRQ_EPPI0_ERR,
106 .end = IRQ_KEY,
134 .end = UART0_RBR+2,
139 .end = IRQ_UART0_TX,
144 .end = IRQ_UART0_RX,
149 .end = IRQ_UART0_ERROR,
154 .end = CH_UART0_TX,
159 .end = CH_UART0_RX,
182 .end = UART1_RBR+2,
187 .end = IRQ_UART1_TX,
[all …]
/arch/avr32/mm/
Dcache.c26 unsigned long v, begin, end, linesz, mask; in invalidate_dcache_region() local
35 end = begin + size; in invalidate_dcache_region()
41 if (end & mask) { in invalidate_dcache_region()
42 flush_dcache_line((void *)end); in invalidate_dcache_region()
43 end &= ~mask; in invalidate_dcache_region()
47 for (v = begin; v < end; v += linesz) in invalidate_dcache_region()
54 unsigned long v, begin, end, linesz; in clean_dcache_region() local
58 end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1); in clean_dcache_region()
60 for (v = begin; v < end; v += linesz) in clean_dcache_region()
67 unsigned long v, begin, end, linesz; in flush_dcache_region() local
[all …]
/arch/m68k/mm/
Dcache.c78 unsigned long start, end; in flush_icache_range() local
80 end = endaddr & ICACHE_SET_MASK; in flush_icache_range()
81 if (start > end) { in flush_icache_range()
82 flush_cf_icache(0, end); in flush_icache_range()
83 end = ICACHE_MAX_ADDR; in flush_icache_range()
85 flush_cf_icache(start, end); in flush_icache_range()
112 unsigned long start, end; in flush_icache_user_range() local
114 end = (addr + len) & ICACHE_SET_MASK; in flush_icache_user_range()
115 if (start > end) { in flush_icache_user_range()
116 flush_cf_icache(0, end); in flush_icache_user_range()
[all …]
/arch/c6x/platforms/
Dcache.c133 unsigned int *end, in cache_block_operation() argument
139 (L2_CACHE_ALIGN_CNT((unsigned int) end) in cache_block_operation()
178 unsigned int *end, in cache_block_operation_nowait() argument
184 (L2_CACHE_ALIGN_CNT((unsigned int) end) in cache_block_operation_nowait()
325 void enable_caching(unsigned long start, unsigned long end) in enable_caching() argument
328 unsigned int mar_e = IMCR_MAR_BASE + ((end >> 24) << 2); in enable_caching()
334 void disable_caching(unsigned long start, unsigned long end) in disable_caching() argument
337 unsigned int mar_e = IMCR_MAR_BASE + ((end >> 24) << 2); in disable_caching()
347 void L1P_cache_block_invalidate(unsigned int start, unsigned int end) in L1P_cache_block_invalidate() argument
350 (unsigned int *) end, in L1P_cache_block_invalidate()
[all …]
/arch/arm/mach-s5pv210/
Ddev-audio.c64 .end = S5PV210_PA_IIS0 + 0x100 - 1,
69 .end = DMACH_I2S0_TX,
74 .end = DMACH_I2S0_RX,
79 .end = DMACH_I2S0S_TX,
111 .end = S5PV210_PA_IIS1 + 0x100 - 1,
116 .end = DMACH_I2S1_TX,
121 .end = DMACH_I2S1_RX,
139 .end = S5PV210_PA_IIS2 + 0x100 - 1,
144 .end = DMACH_I2S2_TX,
149 .end = DMACH_I2S2_RX,
[all …]
/arch/blackfin/mach-bf538/boards/
Dezkit.c48 .end = UART0_GCTL+2,
53 .end = IRQ_UART0_TX,
58 .end = IRQ_UART0_RX,
63 .end = IRQ_UART0_ERROR,
68 .end = CH_UART0_TX,
73 .end = CH_UART0_RX,
79 .end = GPIO_PG7,
84 .end = GPIO_PG6,
108 .end = UART1_GCTL+2,
113 .end = IRQ_UART1_TX,
[all …]
/arch/arm/mach-s5pc100/
Ddev-audio.c61 .end = S5PC100_PA_I2S0 + 0x100 - 1,
66 .end = DMACH_I2S0_TX,
71 .end = DMACH_I2S0_RX,
76 .end = DMACH_I2S0S_TX,
108 .end = S5PC100_PA_I2S1 + 0x100 - 1,
113 .end = DMACH_I2S1_TX,
118 .end = DMACH_I2S1_RX,
136 .end = S5PC100_PA_I2S2 + 0x100 - 1,
141 .end = DMACH_I2S2_TX,
146 .end = DMACH_I2S2_RX,
[all …]
/arch/sparc/include/asm/
Dtlbflush_64.h18 extern void flush_tsb_kernel_range(unsigned long start, unsigned long end);
34 unsigned long start, unsigned long end) in flush_tlb_range() argument
48 extern void __flush_tlb_kernel_range(unsigned long start, unsigned long end);
52 #define flush_tlb_kernel_range(start,end) \ argument
53 do { flush_tsb_kernel_range(start,end); \
54 __flush_tlb_kernel_range(start,end); \
64 extern void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end);
67 #define flush_tlb_kernel_range(start, end) \ argument
68 do { flush_tsb_kernel_range(start,end); \
69 smp_flush_tlb_kernel_range(start, end); \

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