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/arch/ia64/lib/
Dclear_page.S45 .fetch: stf.spill.nta [dst_fetch] = f0, L3_LINE_SIZE
55 1: stf.spill.nta [dst1] = f0, 64
56 stf.spill.nta [dst2] = f0, 64
61 1: stf.spill.nta [dst1] = f0, 64
62 stf.spill.nta [dst2] = f0, 64
63 stf.spill.nta [dst3] = f0, 64
64 stf.spill.nta [dst4] = f0, 128
67 stf.spill.nta [dst1] = f0, 64
68 stf.spill.nta [dst2] = f0, 64
70 stf.spill.nta [dst3] = f0, 64
[all …]
Dmemset.S218 stf.spill [ptr9] = f0, 128 // Do stores one cache line apart
228 stf.spill [ptr2] = f0, 32
229 stf.spill [ptr0] = f0, 32
232 stf.spill [ptr2] = f0, 32
233 stf.spill [ptr0] = f0, 32
236 stf.spill [ptr2] = f0, 32
237 stf.spill [ptr0] = f0, 64
241 stf.spill [ptr2] = f0, 32
242 (p_scr) stf.spill [ptr9] = f0, 128
/arch/sparc/kernel/
Dfpu_traps.S31 fzero %f0
35 faddd %f0, %f2, %f4
36 fmuld %f0, %f2, %f6
37 faddd %f0, %f2, %f8
38 fmuld %f0, %f2, %f10
39 faddd %f0, %f2, %f12
40 fmuld %f0, %f2, %f14
41 faddd %f0, %f2, %f16
42 fmuld %f0, %f2, %f18
43 faddd %f0, %f2, %f20
[all …]
/arch/sparc/lib/
Dclear_page.S75 fzero %f0
80 faddd %f0, %f2, %f4
81 fmuld %f0, %f2, %f6
82 faddd %f0, %f2, %f8
83 fmuld %f0, %f2, %f10
85 faddd %f0, %f2, %f12
86 fmuld %f0, %f2, %f14
87 1: stda %f0, [%o0 + %g0] ASI_BLK_P
DNG2memcpy.S83 faligndata %x0, %x1, %f0; \
93 fmovd %x0, %f0;
95 fmovd %x0, %f0; \
98 fmovd %x0, %f0; \
102 fmovd %x0, %f0; \
107 fmovd %x0, %f0; \
113 fmovd %x0, %f0; \
120 fmovd %x0, %f0; \
128 fmovd %x0, %f0; \
277 EX_LD(LOAD_BLK(%g2, %f0))
[all …]
DU1memcpy.S84 MAIN_LOOP_CHUNK(src, dest, f0, f48, len, branch_dest)
102 #define FINISH_VISCHUNK(dest, f0, f1, left) \ argument
105 faligndata %f0, %f1, %f48; \
109 #define UNEVEN_VISCHUNK_LAST(dest, f0, f1, left) \ argument
112 fsrc1 %f0, %f1;
114 #define UNEVEN_VISCHUNK(dest, f0, f1, left) \ argument
115 UNEVEN_VISCHUNK_LAST(dest, f0, f1, left) \
179 faligndata %f4, %f6, %f0
180 EX_ST(STORE(std, %f0, %o0))
187 faligndata %f6, %f4, %f0
[all …]
Dcopy_page.S101 ldd [%o1 + 0x000], %f0
107 fmovd %f0, %f16
118 ldd [%o1 + 0x040], %f0
125 fmovd %f0, %f16
134 ldd [%o1 + 0x080], %f0
148 fmovd %f0, %f16
176 1: ldda [%o1] ASI_BLK_P, %f0
181 1: TOUCH(f0, f2, f4, f6, f8, f10, f12, f14)
188 ldda [%o1] ASI_BLK_P, %f0
202 TOUCH(f0, f2, f4, f6, f8, f10, f12, f14)
[all …]
DU3memcpy.S139 faligndata %f4, %f6, %f0
140 EX_ST(STORE(std, %f0, %o0))
158 EX_LD(LOAD(ldd, %o1 + 0x000, %f0))
164 faligndata %f0, %f2, %f16
176 EX_LD(LOAD(ldd, %o1 + 0x040, %f0))
190 faligndata %f14, %f0, %f30
193 faligndata %f0, %f2, %f16
206 EX_LD(LOAD(ldd, %o1 + 0x040, %f0))
217 faligndata %f14, %f0, %f30
220 faligndata %f0, %f2, %f16
[all …]
Dxor.S39 ldda [%o1] %asi, %f0
43 fxor %f0, %f16, %f16
53 ldda [%o1 + 128] %asi, %f0
70 fxor %f0, %f16, %f16
110 ldda [%o1] %asi, %f0
114 fxor %f0, %f16, %f48
124 ldda [%o1] %asi, %f0
140 fxor %f0, %f16, %f48
178 ldda [%o1] %asi, %f0
182 fxor %f0, %f16, %f16
[all …]
DVISsave.S66 stda %f0, [%g2 + %g1] ASI_BLK_P
135 stda %f0, [%g2 + %g1] ASI_BLK_P
/arch/x86/boot/
Dcpucheck.c91 u32 f0, f1; in has_eflag() local
103 : "=&r" (f0), "=&r" (f1) in has_eflag()
106 return !!((f0^f1) & mask); in has_eflag()
/arch/mips/include/asm/
Dfpregdef.h23 #define fv0 $f0 /* return value */
62 #define fv0 $f0 /* return value */
Dasmmacro-32.h17 sdc1 $f0, THREAD_FPR0(\thread)
38 swc1 $f0, THREAD_FPR0(\thread)
75 ldc1 $f0, THREAD_FPR0(\thread)
96 lwc1 $f0, THREAD_FPR0(\thread)
Dasmmacro-64.h18 sdc1 $f0, THREAD_FPR0(\thread)
66 ldc1 $f0, THREAD_FPR0(\thread)
/arch/ia64/kernel/
Dhead.S805 stf.spill [sp]=f0 // M3
806 mov f32=f0 // F
811 mov f37=f0 // F
816 mov f40=f0 // F
820 mov f45=f0 // F
824 mov f48=f0 // F
828 mov f53=f0 // F
832 mov f56=f0 // F
836 mov f61=f0 // F
840 mov f64=f0 // F
[all …]
Dentry.S78 stf.spill [sp]=f0
91 mov r4=0; mov f2=f0; mov b1=r0
92 mov r5=0; mov f3=f0; mov b2=r0
93 mov r6=0; mov f4=f0; mov b3=r0
94 mov r7=0; mov f5=f0; mov b4=r0
95 ldf.fill f12=[sp]; mov f13=f0; mov b5=r0
96 ldf.fill f14=[sp]; ldf.fill f15=[sp]; mov f16=f0
97 ldf.fill f17=[sp]; ldf.fill f18=[sp]; mov f19=f0
98 ldf.fill f20=[sp]; ldf.fill f21=[sp]; mov f22=f0
99 ldf.fill f23=[sp]; ldf.fill f24=[sp]; mov f25=f0
[all …]
/arch/cris/configs/
Detrax-100lx_defconfig7 CONFIG_ETRAX_DEF_R_PORT_PA_DATA=f0
/arch/mips/kernel/
Dr6000_fpu.S31 sdc1 $f0,(SC_FPREGS+0)(a0)
68 ldc1 $f0,(SC_FPREGS+0)(a0)
Dr4k_fpu.S60 EX sdc1 $f0, SC_FPREGS+0(a0)
86 EX sdc1 $f0, SC32_FPREGS+0(a0)
136 EX ldc1 $f0, SC_FPREGS+0(a0)
161 EX ldc1 $f0, SC32_FPREGS+0(a0)
Dr2300_fpu.S33 EX(swc1 $f0,(SC_FPREGS+0)(a0))
85 EX(lwc1 $f0,(SC_FPREGS+0)(a0))
Dr4k_switch.S201 mtc1 t1, $f0
235 dmtc1 t1, $f0
Dr2300_switch.S138 mtc1 t0, $f0
/arch/unicore32/kernel/
Dhibernate_asm.S77 lfm.w (f0 - f7 ), [ip]+
108 sfm.w (f0 - f7 ), [ip]+
Dsleep.S57 sfm.w (f0 - f7 ), [sp-]
194 lfm.w (f0 - f7 ), [sp]+
/arch/alpha/kernel/
Dentry.S495 stt $f0, 64($sp)
523 mf_fpcr $f0 # get fpcr
527 stt $f0, 312($sp) # save fpcr in slot of $f31
528 ldt $f0, 64($sp) # dont let "do_switch_stack" change fp state.
544 ldt $f0, 64($sp)

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