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/arch/ia64/lib/
Didiv32.S59 frcpa.s1 f6, p6 = f8, f9 // y0 = frcpa(b)
61 (p6) fmpy.s1 f8 = f8, f6 // q0 = a*y0
62 (p6) fnma.s1 f6 = f9, f6, f1 // e0 = -b*y0 + 1
67 (p6) fma.s1 f8 = f6, f8, f8 // q1 = e0*q0 + q0
68 (p6) fma.s1 f6 = f6, f6, f7 // e1 = e0*e0 + 2^-34
73 (p6) fma.s1 f6 = f6, f8, f8 // q2 = e1*q1 + q1
75 FP_TO_INT(f6, f6) // q = trunc(q2)
78 xma.l f6 = f6, f9, f7 // r = q*(-b) + a
81 getf.sig r8 = f6 // transfer result to result register
Didiv64.S52 (p6) fnma.s1 f6 = f9, f11, f1 // e0 = -b*y0 + 1
54 (p6) fma.s1 f10 = f7, f6, f7 // q1 = q0*e0 + q0
55 (p6) fmpy.s1 f7 = f6, f6 // e1 = e0*e0
61 (p6) fma.s1 f6 = f11, f6, f11 // y1 = y0*e0 + y0
63 (p6) fma.s1 f6 = f6, f7, f6 // y2 = y1*e1 + y1
70 (p6) fma.s1 f11 = f7, f6, f10 // q3 = r*y2 + q2
Dmemcpy_mck.S76 mov f6=f0
86 mov f6=f1
598 fcmp.eq p8,p0=f6,f0 // is it memcpy?
/arch/sparc/lib/
DU1memcpy.S65 #define FREG_FROB(f1, f2, f3, f4, f5, f6, f7, f8, f9) \ argument
70 faligndata %f5, %f6, %f56; \
71 faligndata %f6, %f7, %f58; \
176 1: EX_LD(LOAD(ldd, %o1 + 0x8, %f6))
179 faligndata %f4, %f6, %f0
187 faligndata %f6, %f4, %f0
236 1: FREG_FROB(f0, f2, f4, f6, f8, f10,f12,f14,f16)
250 FREG_FROB(f0, f2, f4, f6, f8, f10,f12,f14,f16)
252 3: FREG_FROB(f0, f2, f4, f6, f8, f10,f12,f14,f16)
257 1: FREG_FROB(f2, f4, f6, f8, f10,f12,f14,f16,f18)
[all …]
Dcopy_page.S108 ldd [%o1 + 0x018], %f6
113 fmovd %f6, %f22
124 ldd [%o1 + 0x058], %f6
131 fmovd %f6, %f22
147 ldd [%o1 + 0x058], %f6
154 fmovd %f6, %f22
181 1: TOUCH(f0, f2, f4, f6, f8, f10, f12, f14)
202 TOUCH(f0, f2, f4, f6, f8, f10, f12, f14)
DU3memcpy.S136 1: EX_LD(LOAD(ldd, %o1 + 0x8, %f6))
139 faligndata %f4, %f6, %f0
147 faligndata %f6, %f4, %f2
165 EX_LD(LOAD(ldd, %o1 + 0x018, %f6))
168 faligndata %f4, %f6, %f20
170 faligndata %f6, %f8, %f22
192 EX_LD(LOAD(ldd, %o1 + 0x018, %f6))
199 faligndata %f4, %f6, %f20
202 faligndata %f6, %f8, %f22
219 EX_LD(LOAD(ldd, %o1 + 0x018, %f6))
[all …]
DNG2memcpy.S86 faligndata %x3, %x4, %f6; \
105 fmovd %x3, %f6;
110 fmovd %x3, %f6; \
116 fmovd %x3, %f6; \
123 fmovd %x3, %f6; \
131 fmovd %x3, %f6; \
280 FREG_FROB(f0, f2, f4, f6, f8, f10, f12, f14, f16)
291 FREG_LOAD_7(%g2, f0, f2, f4, f6, f8, f10, f12)
294 FREG_FROB(f0, f2, f4, f6, f8, f10, f12, f16, f18)
305 FREG_LOAD_6(%g2, f0, f2, f4, f6, f8, f10)
[all …]
Dxor.S46 fxor %f6, %f22, %f22
73 fxor %f6, %f22, %f22
118 fxor %f6, %f22, %f54
143 fxor %f6, %f22, %f54
186 fxor %f6, %f22, %f22
221 fxor %f6, %f22, %f22
274 fxor %f6, %f22, %f54
319 fxor %f6, %f22, %f54
Dclear_page.S81 fmuld %f0, %f2, %f6
/arch/mips/include/asm/
Dfpregdef.h33 #define ft1 $f6
74 #define ft2 $f6
Dasmmacro-32.h20 sdc1 $f6, THREAD_FPR6(\thread)
44 swc1 $f6, THREAD_FPR6(\thread)
78 ldc1 $f6, THREAD_FPR6(\thread)
102 lwc1 $f6, THREAD_FPR6(\thread)
Dasmmacro-64.h21 sdc1 $f6, THREAD_FPR6(\thread)
69 ldc1 $f6, THREAD_FPR6(\thread)
/arch/ia64/kernel/
Dgate.S148 stf.spill [base0]=f6,32
176 ldf.fill f6=[base0],32
274 setf.sig f6=r18
276 xmpy.h f6=f6,f7
278 getf.sig r17=f6
Dprocess.c129 regs->f6.u.bits[1], regs->f6.u.bits[0], in show_regs()
/arch/mips/kernel/
Dr6000_fpu.S34 sdc1 $f6,(SC_FPREGS+48)(a0)
71 ldc1 $f6,(SC_FPREGS+48)(a0)
Dr4k_fpu.S63 EX sdc1 $f6, SC_FPREGS+48(a0)
89 EX sdc1 $f6, SC32_FPREGS+48(a0)
139 EX ldc1 $f6, SC_FPREGS+48(a0)
164 EX ldc1 $f6, SC32_FPREGS+48(a0)
Dr2300_fpu.S39 EX(swc1 $f6,(SC_FPREGS+48)(a0))
91 EX(lwc1 $f6,(SC_FPREGS+48)(a0))
Dr4k_switch.S207 mtc1 t1, $f6
238 dmtc1 t1, $f6
Dr2300_switch.S144 mtc1 t0, $f6
/arch/sparc/kernel/
Dfpu_traps.S36 fmuld %f0, %f2, %f6
68 fmuld %f0, %f2, %f6
255 fitod %f6, %f62
298 fdtos %f62, %f6
/arch/ia64/include/asm/
Dptrace.h168 struct ia64_fpreg f6; /* scratch */ member
Dkvm_host.h559 struct ia64_fpreg f6; /* scratch */ member
/arch/xtensa/variants/s6000/include/variant/
Dtie.h109 XCHAL_SA_REG(s,0,0,2,0, f6, 4, 4, 4,0x0036, f,6 , 32,0,0,0) \
Dtie-asm.h88 SSI f6, \ptr, 32
122 LSI f6, \ptr, 32
/arch/s390/kernel/
Dreipl64.S37 std %f6, 0x30 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)

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