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Searched refs:hclk (Results 1 – 22 of 22) sorted by relevance

/arch/arm/mach-s3c2412/
Dcpu-freq.c38 static struct clk *hclk; variable
46 unsigned long hclk, fclk, armclk, armdiv_clk; in s3c2412_cpufreq_calcdivs() local
51 hclk_max = cfg->max.hclk; in s3c2412_cpufreq_calcdivs()
63 cfg->freq.hclk, cfg->freq.pclk); in s3c2412_cpufreq_calcdivs()
79 cfg->freq.hclk = hclk = armdiv_clk / hdiv; in s3c2412_cpufreq_calcdivs()
85 cfg->freq.armclk = dvs ? hclk : armdiv_clk; in s3c2412_cpufreq_calcdivs()
88 __func__, armclk, hclk, armdiv, hdiv, cfg->divs.dvs); in s3c2412_cpufreq_calcdivs()
93 pdiv = (hclk > cfg->max.pclk) ? 2 : 1; in s3c2412_cpufreq_calcdivs()
95 if ((hclk / pdiv) > cfg->max.pclk) in s3c2412_cpufreq_calcdivs()
98 cfg->freq.pclk = hclk / pdiv; in s3c2412_cpufreq_calcdivs()
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/arch/arm/mach-s3c2440/
Ds3c2440-cpufreq.c39 static struct clk *hclk; variable
62 unsigned long hclk, fclk, armclk; in s3c2440_cpufreq_calcdivs() local
67 hclk_max = cfg->max.hclk; in s3c2440_cpufreq_calcdivs()
85 hclk = (fclk / hdiv); in s3c2440_cpufreq_calcdivs()
86 if (hclk <= hclk_max || within_khz(hclk, hclk_max)) in s3c2440_cpufreq_calcdivs()
90 s3c_freq_dbg("%s: hclk %lu, div %d\n", __func__, hclk, hdiv); in s3c2440_cpufreq_calcdivs()
95 pdiv = (hclk > cfg->max.pclk) ? 2 : 1; in s3c2440_cpufreq_calcdivs()
97 if ((hclk / pdiv) > cfg->max.pclk) in s3c2440_cpufreq_calcdivs()
109 if (armclk < hclk) in s3c2440_cpufreq_calcdivs()
110 armclk = hclk; in s3c2440_cpufreq_calcdivs()
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/arch/arm/mach-s3c2410/
Dcpu-freq.c50 unsigned long hclk, fclk, pclk; in s3c2410_cpufreq_calcdivs() local
55 hclk_max = cfg->max.hclk; in s3c2410_cpufreq_calcdivs()
62 hdiv = (fclk > cfg->max.hclk) ? 2 : 1; in s3c2410_cpufreq_calcdivs()
63 hclk = fclk / hdiv; in s3c2410_cpufreq_calcdivs()
65 if (hclk > cfg->max.hclk) { in s3c2410_cpufreq_calcdivs()
70 pdiv = (hclk > cfg->max.pclk) ? 2 : 1; in s3c2410_cpufreq_calcdivs()
71 pclk = hclk / pdiv; in s3c2410_cpufreq_calcdivs()
90 .hclk = 100000000,
145 s3c2410_cpufreq_info.max.hclk = 133000000; in s3c2410a_cpufreq_add()
/arch/arm/plat-s3c24xx/
Ds3c2410-iotiming.c136 int calc_tacp(unsigned int cyc, unsigned long hclk, unsigned long *v) in calc_tacp() argument
220 unsigned long hclk = cfg->freq.hclk_tns; in s3c2410_calc_bank() local
234 ret = calc_0124(bt->tacs, hclk, &res, S3C2410_BANKCON_Tacs_SHIFT); in s3c2410_calc_bank()
235 ret |= calc_0124(bt->tcos, hclk, &res, S3C2410_BANKCON_Tcos_SHIFT); in s3c2410_calc_bank()
236 ret |= calc_0124(bt->tcah, hclk, &res, S3C2410_BANKCON_Tcah_SHIFT); in s3c2410_calc_bank()
237 ret |= calc_0124(bt->tcoh, hclk, &res, S3C2410_BANKCON_Tcoh_SHIFT); in s3c2410_calc_bank()
242 ret |= calc_tacp(bt->tacp, hclk, &res); in s3c2410_calc_bank()
243 ret |= calc_tacc(bt->tacc, bt->nwait_en, hclk, &res); in s3c2410_calc_bank()
299 unsigned long hclk = cfg->freq.hclk_tns; in s3c2410_iotiming_getbank() local
301 bt->tcah = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcah_SHIFT); in s3c2410_iotiming_getbank()
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Ds3c2412-iotiming.c100 unsigned int hclk = cfg->freq.hclk_tns; in s3c2412_calc_bank() local
103 bt->smbidcyr = calc_timing(bt->idcy, hclk, &err); in s3c2412_calc_bank()
104 bt->smbwstrd = calc_timing(bt->wstrd, hclk, &err); in s3c2412_calc_bank()
105 bt->smbwstwr = calc_timing(bt->wstwr, hclk, &err); in s3c2412_calc_bank()
106 bt->smbwstoen = calc_timing(bt->wstoen, hclk, &err); in s3c2412_calc_bank()
107 bt->smbwstwen = calc_timing(bt->wstwen, hclk, &err); in s3c2412_calc_bank()
108 bt->smbwstbrd = calc_timing(bt->wstbrd, hclk, &err); in s3c2412_calc_bank()
279 refresh = (cfg->freq.hclk / 100) * (board->refresh / 10); in s3c2412_cpufreq_setrefresh()
Dcpu-freq.c67 unsigned long fclk, pclk, hclk, armclk; in s3c_cpufreq_getcur() local
70 cfg->freq.hclk = hclk = clk_get_rate(clk_hclk); in s3c_cpufreq_getcur()
77 cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10); in s3c_cpufreq_getcur()
79 cfg->divs.h_divisor = fclk / hclk; in s3c_cpufreq_getcur()
88 cfg->freq.hclk = pll / cfg->divs.h_divisor; in s3c_cpufreq_calc()
92 cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10); in s3c_cpufreq_calc()
108 cfg->freq.hclk, cfg->divs.h_divisor, in s3c_cpufreq_show()
194 if (cpu_new.freq.hclk != cpu_cur.freq.hclk) { in s3c_cpufreq_settarget()
218 s3c_cpufreq_updateclk(clk_hclk, cpu_new.freq.hclk); in s3c_cpufreq_settarget()
233 if (cpu_new.freq.hclk < cpu_cur.freq.hclk) { in s3c_cpufreq_settarget()
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Dclock.c49 unsigned long hclk, in s3c24xx_setup_clocks() argument
56 clk_h.rate = hclk; in s3c24xx_setup_clocks()
Dcpu-freq-debugfs.c35 f->fclk, f->hclk, f->pclk, f->armclk); in show_max()
90 cfg->freq.hclk, print_ns(cfg->freq.hclk_tns)); in info_show()
91 seq_printf(seq, " PCLK %ld Hz\n", cfg->freq.hclk); in info_show()
Ds3c2410-cpufreq-utils.c45 refresh = (cfg->freq.hclk / 100) * (board->refresh / 10); in s3c2410_cpufreq_setrefresh()
/arch/avr32/mach-at32ap/
Dpdc.c16 struct clk *pclk, *hclk; in pdc_probe() local
23 hclk = clk_get(&pdev->dev, "hclk"); in pdc_probe()
24 if (IS_ERR(hclk)) { in pdc_probe()
27 return PTR_ERR(hclk); in pdc_probe()
31 clk_enable(hclk); in pdc_probe()
Dat32ap700x.c615 DEV_CLK(hclk, dw_dmac0, hsb, 10);
720 DEV_CLK(hclk, pdc, hsb, 4);
1074 DEV_CLK(hclk, macb0, hsb, 8);
1083 DEV_CLK(hclk, macb1, hsb, 9);
/arch/arm/mach-mv78xx0/
Dcommon.c48 int hclk; in get_hclk() local
55 hclk = 166666667; in get_hclk()
58 hclk = 200000000; in get_hclk()
61 hclk = 266666667; in get_hclk()
64 hclk = 333333333; in get_hclk()
67 hclk = 400000000; in get_hclk()
74 return hclk; in get_hclk()
77 static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk) in get_pclk_l2clk() argument
95 *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1; in get_pclk_l2clk()
378 int hclk; in mv78xx0_init() local
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/arch/arm/mach-s3c24xx/
Ds3c2412.c179 unsigned long hclk; in s3c2412_setup_clocks() local
197 hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1); in s3c2412_setup_clocks()
198 hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1); in s3c2412_setup_clocks()
199 pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1); in s3c2412_setup_clocks()
204 print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); in s3c2412_setup_clocks()
206 s3c24xx_setup_clocks(fclk, hclk, pclk); in s3c2412_setup_clocks()
Ds3c2410.c89 unsigned long hclk; in s3c2410_setup_clocks() local
105 hclk = fclk / ((tmp & S3C2410_CLKDIVN_HDIVN) ? 2 : 1); in s3c2410_setup_clocks()
106 pclk = hclk / ((tmp & S3C2410_CLKDIVN_PDIVN) ? 2 : 1); in s3c2410_setup_clocks()
111 print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); in s3c2410_setup_clocks()
117 s3c24xx_setup_clocks(fclk, hclk, pclk); in s3c2410_setup_clocks()
Ds3c244x.c86 unsigned long hclk, fclk, pclk; in s3c244x_setup_clocks() local
118 hclk = fclk / hdiv; in s3c244x_setup_clocks()
119 pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1); in s3c244x_setup_clocks()
124 print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); in s3c244x_setup_clocks()
126 s3c24xx_setup_clocks(fclk, hclk, pclk); in s3c244x_setup_clocks()
Dmach-osiris-dvs.c48 return f->armclk == f->hclk; in is_dvs()
67 freqs->old.armclk, freqs->old.hclk, in osiris_dvs_notify()
68 freqs->new.armclk, freqs->new.hclk); in osiris_dvs_notify()
/arch/arm/mach-imx/
Dclock-imx1.c268 static struct clk hclk = { variable
451 &hclk,
487 .parent = &hclk,
497 .parent = &hclk,
507 .parent = &hclk,
539 .parent = &hclk,
563 .parent = &hclk,
629 clk_enable(&hclk); in mx1_clocks_init()
/arch/arm/plat-samsung/include/plat/
Dcpu-freq.h39 unsigned long hclk; member
Dclock.h115 unsigned long hclk,
/arch/arm/mach-s5p64x0/
Dclock-s5p6440.c535 unsigned long hclk; in s5p6440_setup_clocks() local
572 hclk = clk_get_rate(&clk_hclk.clk); in s5p6440_setup_clocks()
579 print_mhz(hclk), print_mhz(hclk_low), in s5p6440_setup_clocks()
583 clk_h.rate = hclk; in s5p6440_setup_clocks()
Dclock-s5p6450.c601 unsigned long hclk; in s5p6450_setup_clocks() local
643 hclk = clk_get_rate(&clk_hclk.clk); in s5p6450_setup_clocks()
650 print_mhz(hclk), print_mhz(hclk_low), in s5p6450_setup_clocks()
654 clk_h.rate = hclk; in s5p6450_setup_clocks()
/arch/arm/mach-s3c64xx/
Dclock.c874 unsigned long hclk; in s3c64xx_setup_clocks() local
916 hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK); in s3c64xx_setup_clocks()
920 hclk2, hclk, pclk); in s3c64xx_setup_clocks()
927 clk_h.rate = hclk; in s3c64xx_setup_clocks()