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Searched refs:in_be32 (Results 1 – 25 of 92) sorted by relevance

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/arch/powerpc/sysdev/qe_lib/
Dqe_io.c65 tmp_val = in_be32(&par_io->cpodr); in __par_io_config_pin()
73 in_be32(&par_io->cpdir2) : in __par_io_config_pin()
74 in_be32(&par_io->cpdir1); in __par_io_config_pin()
98 in_be32(&par_io->cppar2) : in __par_io_config_pin()
99 in_be32(&par_io->cppar1); in __par_io_config_pin()
141 tmp_val = in_be32(&par_io[port].cpdata); in par_io_data_set()
203 in_be32(&par_io[i].cpodr)); in dump_par_io()
205 in_be32(&par_io[i].cpdata)); in dump_par_io()
207 in_be32(&par_io[i].cpdir1)); in dump_par_io()
209 in_be32(&par_io[i].cpdir2)); in dump_par_io()
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Ducc_fast.c37 &uccf->uf_regs->gumr, in_be32(&uccf->uf_regs->gumr)); in ucc_fast_dump_regs()
39 &uccf->uf_regs->upsmr, in_be32(&uccf->uf_regs->upsmr)); in ucc_fast_dump_regs()
45 &uccf->uf_regs->ucce, in_be32(&uccf->uf_regs->ucce)); in ucc_fast_dump_regs()
47 &uccf->uf_regs->uccm, in_be32(&uccf->uf_regs->uccm)); in ucc_fast_dump_regs()
51 &uccf->uf_regs->urfb, in_be32(&uccf->uf_regs->urfb)); in ucc_fast_dump_regs()
59 &uccf->uf_regs->utfb, in_be32(&uccf->uf_regs->utfb)); in ucc_fast_dump_regs()
69 &uccf->uf_regs->urtry, in_be32(&uccf->uf_regs->urtry)); in ucc_fast_dump_regs()
105 gumr = in_be32(&uf_regs->gumr); in ucc_fast_enable()
126 gumr = in_be32(&uf_regs->gumr); in ucc_fast_disable()
Dgpio.c51 qe_gc->cpdata = in_be32(&regs->cpdata); in qe_gpio_save_regs()
53 qe_gc->saved_regs.cpdir1 = in_be32(&regs->cpdir1); in qe_gpio_save_regs()
54 qe_gc->saved_regs.cpdir2 = in_be32(&regs->cpdir2); in qe_gpio_save_regs()
55 qe_gc->saved_regs.cppar1 = in_be32(&regs->cppar1); in qe_gpio_save_regs()
56 qe_gc->saved_regs.cppar2 = in_be32(&regs->cppar2); in qe_gpio_save_regs()
57 qe_gc->saved_regs.cpodr = in_be32(&regs->cpodr); in qe_gpio_save_regs()
66 return in_be32(&regs->cpdata) & pin_mask; in qe_gpio_get()
/arch/powerpc/platforms/powernv/
Dpci-p5ioc2.c147 pr_devel(" P_BUID = 0x%08x\n", in_be32(phb->regs + 0x100)); in pnv_pci_init_p5ioc2_phb()
148 pr_devel(" P_IOSZ = 0x%08x\n", in_be32(phb->regs + 0x1b0)); in pnv_pci_init_p5ioc2_phb()
149 pr_devel(" P_IO_ST = 0x%08x\n", in_be32(phb->regs + 0x1e0)); in pnv_pci_init_p5ioc2_phb()
150 pr_devel(" P_MEM1_H = 0x%08x\n", in_be32(phb->regs + 0x1a0)); in pnv_pci_init_p5ioc2_phb()
151 pr_devel(" P_MEM1_L = 0x%08x\n", in_be32(phb->regs + 0x190)); in pnv_pci_init_p5ioc2_phb()
152 pr_devel(" P_MSZ1_L = 0x%08x\n", in_be32(phb->regs + 0x1c0)); in pnv_pci_init_p5ioc2_phb()
153 pr_devel(" P_MEM_ST = 0x%08x\n", in_be32(phb->regs + 0x1d0)); in pnv_pci_init_p5ioc2_phb()
154 pr_devel(" P_MEM2_H = 0x%08x\n", in_be32(phb->regs + 0x2c0)); in pnv_pci_init_p5ioc2_phb()
155 pr_devel(" P_MEM2_L = 0x%08x\n", in_be32(phb->regs + 0x2b0)); in pnv_pci_init_p5ioc2_phb()
156 pr_devel(" P_MSZ2_H = 0x%08x\n", in_be32(phb->regs + 0x2d0)); in pnv_pci_init_p5ioc2_phb()
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/arch/powerpc/platforms/cell/
Dcelleb_scc_epci.c75 out_be32(reg, in_be32(reg) | (PCI_STATUS_REC_MASTER_ABORT << 16)); in clear_and_disable_master_abort_interrupt()
89 val = in_be32(reg); in celleb_epci_check_abort()
100 val = in_be32(reg) & 0xffff; in celleb_epci_check_abort()
159 *val = in_be32(addr); in celleb_epci_read_config()
265 val = in_be32(reg); in celleb_epci_init()
273 val = in_be32(reg); in celleb_epci_init()
278 val = in_be32(reg); in celleb_epci_init()
284 val = in_be32(reg); in celleb_epci_init()
295 val = in_be32(reg); in celleb_epci_init()
300 val = in_be32(reg); in celleb_epci_init()
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Dspider-pic.c87 out_be32(cfg, in_be32(cfg) | 0x30000000u); in spider_unmask_irq()
95 out_be32(cfg, in_be32(cfg) & ~0x30000000u); in spider_mask_irq()
155 old_mask = in_be32(cfg) & 0x30000000u; in spider_set_irq_type()
208 cs = in_be32(pic->regs + TIR_CS) >> 24; in spider_irq_cascade()
310 out_be32(cfg, in_be32(cfg) & ~0x30000000u); in spider_init_one()
317 out_be32(pic->regs + TIR_PIEN, in_be32(pic->regs + TIR_PIEN) | 0x1); in spider_init_one()
330 out_be32(pic->regs + TIR_DEN, in_be32(pic->regs + TIR_DEN) | 0x1); in spider_init_one()
Dcelleb_scc_uhc.c79 while (!uhc_clkctrl_ready(in_be32(uhc_clkctrl))) { in enable_scc_uhc()
83 in_be32(uhc_clkctrl)); in enable_scc_uhc()
/arch/powerpc/boot/
Duartlite.c42 reg = in_be32(reg_base + ULITE_STATUS); in uartlite_putc()
50 reg = in_be32(reg_base + ULITE_STATUS); in uartlite_getc()
51 return in_be32(reg_base + ULITE_RX); in uartlite_getc()
56 u32 reg = in_be32(reg_base + ULITE_STATUS); in uartlite_tstc()
Dpq2.c44 sccr = in_be32(&immr[PQ2_SCCR]); in pq2_get_clocks()
45 scmr = in_be32(&immr[PQ2_SCMR]); in pq2_get_clocks()
Dcpm-serial.c100 while (in_be32(cpcr) & 0x10000) in cpm2_cmd()
105 while (in_be32(cpcr) & 0x10000) in cpm2_cmd()
118 out_be32(&scc->gsmrl, in_be32(&scc->gsmrl) & ~0x30); in scc_disable_port()
129 out_be32(&scc->gsmrl, in_be32(&scc->gsmrl) | 0x30); in scc_enable_port()
Dugecon.c60 while (in_be32(cr_reg) & EXI_CR_TSTART) in ug_io_transaction()
66 data = in_be32(data_reg); in ug_io_transaction()
/arch/powerpc/platforms/cell/spufs/
Dhw_ops.c45 mbox_stat = in_be32(&prob->mb_stat_R); in spu_hw_mbox_read()
47 *data = in_be32(&prob->pu_mb_R); in spu_hw_mbox_read()
56 return in_be32(&ctx->spu->problem->mb_stat_R); in spu_hw_mbox_stat_read()
67 stat = in_be32(&spu->problem->mb_stat_R); in spu_hw_mbox_stat_poll()
104 if (in_be32(&prob->mb_stat_R) & 0xff0000) { in spu_hw_ibox_read()
124 if (in_be32(&prob->mb_stat_R) & 0x00ff00) { in spu_hw_wbox_write()
192 return in_be32(&ctx->spu->problem->spu_npc_RW); in spu_hw_npc_read()
202 return in_be32(&ctx->spu->problem->spu_status_R); in spu_hw_status_read()
217 return in_be32(&ctx->spu->problem->spu_runcntl_RW); in spu_hw_runcntl_read()
234 while (in_be32(&ctx->spu->problem->spu_status_R) & SPU_STATUS_RUNNING) in spu_hw_runcntl_stop()
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Dswitch.c108 return (in_be32(&prob->spu_status_R) & isolate_state) ? 1 : 0; in check_spu_isolate()
223 csa->prob.spu_runcntl_RW = in_be32(&prob->spu_runcntl_RW); in save_spu_runcntl()
241 if ((in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) == 0) { in save_spu_status()
242 csa->prob.spu_status_R = in_be32(&prob->spu_status_R); in save_spu_status()
248 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & in save_spu_status()
253 if ((in_be32(&prob->spu_status_R) & stopped) == 0) in save_spu_status()
256 csa->prob.spu_status_R = in_be32(&prob->spu_status_R); in save_spu_status()
388 csa->prob.dma_querymask_RW = in_be32(&prob->dma_querymask_RW); in save_ppu_querymask()
399 csa->prob.dma_querytype_RW = in_be32(&prob->dma_querytype_RW); in save_ppu_querytype()
412 csa->prob.dma_tagstatus_R = in_be32(&prob->dma_tagstatus_R); in save_ppu_tagstatus()
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/arch/powerpc/platforms/83xx/
Dsuspend.c125 u32 reg_cfg1 = in_be32(&pmc_regs->config1); in mpc83xx_change_state()
147 u32 event = in_be32(&pmc_regs->event); in pmc_irq_handler()
170 saved_regs.sicrl = in_be32(&syscr_regs->sicrl); in mpc83xx_suspend_save_regs()
171 saved_regs.sicrh = in_be32(&syscr_regs->sicrh); in mpc83xx_suspend_save_regs()
172 saved_regs.sccr = in_be32(&clock_regs->sccr); in mpc83xx_suspend_save_regs()
188 in_be32(&pmc_regs->config1) | PMCCR1_PME_EN); in mpc83xx_suspend_enter()
209 in_be32(&pmc_regs->config1) | PMCCR1_POWER_OFF); in mpc83xx_suspend_enter()
216 in_be32(&pmc_regs->config1) & ~PMCCR1_POWER_OFF); in mpc83xx_suspend_enter()
231 in_be32(&pmc_regs->config1) & ~PMCCR1_PME_EN); in mpc83xx_suspend_enter()
310 ret = !(in_be32(&rcw_regs->rcwhr) & RCW_PCI_HOST); in mpc83xx_is_pci_agent()
/arch/powerpc/platforms/52xx/
Dlite5200.c74 if (in_be32(&cdm->rstcfg) & 0x40) /* Assumes 33Mhz clock */ in lite5200_fix_clock_config()
107 port_config = in_be32(&gpio->port_config); in lite5200_fix_port_config()
118 in_be32(&gpio->port_config), port_config); in lite5200_fix_port_config()
139 out_be32(mbar + 0x1048, in_be32(mbar + 0x1048) & ~0x300); in lite5200_suspend_prepare()
Dmedia5200.c58 val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE); in media5200_irq_unmask()
70 val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE); in media5200_irq_mask()
96 status = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE); in media5200_irq_cascade()
97 enable = in_be32(media5200_irq.regs + MEDIA5200_IRQ_STATUS); in media5200_irq_cascade()
222 port_config = in_be32(&gpio->port_config); in media5200_setup_arch()
Dmpc52xx_pic.c147 out_be32(addr, in_be32(addr) | (1 << bitno)); in io_be_setbit()
152 out_be32(addr, in_be32(addr) & ~(1 << bitno)); in io_be_clrbit()
194 ctrl_reg = in_be32(&intr->ctrl); in mpc52xx_extirq_set_type()
356 reg = in_be32(&intr->ctrl); in mpc52xx_irqhost_map()
428 intr_ctrl = in_be32(&intr->ctrl); in mpc52xx_init_irq()
491 status = in_be32(&intr->enc_status); in mpc52xx_get_irq()
506 status = in_be32(&sdma->IntPend); in mpc52xx_get_irq()
Dmpc52xx_common.c83 out_be32(&xlb->config, in_be32(&xlb->config) | MPC52xx_XLB_CFG_PLDIS); in mpc5200_setup_xlb_arbiter()
198 val = in_be32(&mpc52xx_cdm->clk_enables); in mpc52xx_set_psc_clkdiv()
229 val = in_be32(&mpc52xx_cdm->rstcfg); in mpc52xx_get_xtal_freq()
313 mux = in_be32(&simple_gpio->port_config); in mpc5200_psc_ac97_gpio_reset()
/arch/powerpc/sysdev/
Dfsl_ifc.c66 __be32 cspr = in_be32(&fsl_ifc_ctrl_dev->regs->cspr_cs[i].cspr); in fsl_ifc_find()
83 if (in_be32(&ifc->cm_evter_stat) & IFC_CM_EVTER_STAT_CSER) in fsl_ifc_ctrl_init()
131 stat = in_be32(&ifc->ifc_nand.nand_evter_stat); in check_nand_stat()
165 cs_err = in_be32(&ifc->cm_evter_stat); in fsl_ifc_ctrl_irq()
173 status = in_be32(&ifc->cm_erattr0); in fsl_ifc_ctrl_irq()
174 err_addr = in_be32(&ifc->cm_erattr1); in fsl_ifc_ctrl_irq()
Dfsl_rmu.c212 osr = in_be32(&rmu->msg_regs->osr); in fsl_rio_tx_handler()
227 u32 dqp = in_be32(&rmu->msg_regs->odqdpar); in fsl_rio_tx_handler()
257 isr = in_be32(&rmu->msg_regs->isr); in fsl_rio_rx_handler()
300 dsr = in_be32(&fsl_dbell->dbell_regs->dsr); in fsl_rio_dbell_handler()
317 (in_be32(&fsl_dbell->dbell_regs->dqdpar) & 0xfff); in fsl_rio_dbell_handler()
395 epwisr = in_be32(rio_regs_win + RIO_EPWISR); in fsl_rio_port_write_handler()
399 ipwmr = in_be32(&pw->pw_regs->pwmr); in fsl_rio_port_write_handler()
400 ipwsr = in_be32(&pw->pw_regs->pwsr); in fsl_rio_port_write_handler()
460 tmp = in_be32(rio_regs_win + RIO_LTLEDCSR); in fsl_rio_port_write_handler()
466 tmp = in_be32(rio_regs_win + RIO_LTLEDCSR); in fsl_rio_port_write_handler()
[all …]
/arch/powerpc/sysdev/ge/
Dge_pic.c118 mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0)); in gef_pic_mask()
139 mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0)); in gef_pic_unmask()
234 cause = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_STATUS); in gef_pic_get_irq()
236 mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0)); in gef_pic_get_irq()
/arch/powerpc/platforms/85xx/
Dp1022_ds.c185 u64 lawbar = in_be32(&law[i].lawbar); in lbc_br_to_phys()
186 u32 lawar = in_be32(&law[i].lawar); in lbc_br_to_phys()
270 br0 = in_be32(&lbc->bank[0].br); in p1022ds_set_monitor_port()
271 br1 = in_be32(&lbc->bank[1].br); in p1022ds_set_monitor_port()
272 or0 = in_be32(&lbc->bank[0].or); in p1022ds_set_monitor_port()
273 or1 = in_be32(&lbc->bank[1].or); in p1022ds_set_monitor_port()
326 if ((in_be32(&guts->pmuxcr) & PMUXCR_ELBCDIU_MASK) != in p1022ds_set_monitor_port()
358 in_be32(&guts->pmuxcr); in p1022ds_set_monitor_port()
/arch/powerpc/platforms/512x/
Dpdm360ng.c37 reg = in_be32(pdm360ng_gpio_base + 0xc); in pdm360ng_get_pendown_state()
41 reg = in_be32(pdm360ng_gpio_base + 0x8); in pdm360ng_get_pendown_state()
/arch/microblaze/kernel/
Dtimer.c64 out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0) & ~TCSR_ENT); in microblaze_timer0_stop()
149 out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0)); in timer_ack()
186 return (cycle_t) (in_be32(TIMER_BASE + TCR1)); in microblaze_read()
228 out_be32(TIMER_BASE + TCSR1, in_be32(TIMER_BASE + TCSR1) & ~TCSR_ENT); in microblaze_clocksource_init()
/arch/powerpc/platforms/44x/
Dwarp.c85 post1 = in_be32(fpga + 0x40); in warp_post_info()
86 post2 = in_be32(fpga + 0x44); in warp_post_info()
160 unsigned reset = in_be32(dtm_fpga + 0x14); in temp_isr()
225 u32 fan = in_be32(fpga + 0x34) & (1 << 14); in pika_dtm_check_fan()

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