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/arch/arm/mach-s3c2440/
Ds3c2440-pll-16934400.c25 { .frequency = 78019200, .index = PLLVAL(121, 5, 3), }, /* FVco 624.153600 */
26 { .frequency = 84067200, .index = PLLVAL(131, 5, 3), }, /* FVco 672.537600 */
27 { .frequency = 90115200, .index = PLLVAL(141, 5, 3), }, /* FVco 720.921600 */
28 { .frequency = 96163200, .index = PLLVAL(151, 5, 3), }, /* FVco 769.305600 */
29 { .frequency = 102135600, .index = PLLVAL(185, 6, 3), }, /* FVco 817.084800 */
30 { .frequency = 108259200, .index = PLLVAL(171, 5, 3), }, /* FVco 866.073600 */
31 { .frequency = 114307200, .index = PLLVAL(127, 3, 3), }, /* FVco 914.457600 */
32 { .frequency = 120234240, .index = PLLVAL(134, 3, 3), }, /* FVco 961.873920 */
33 { .frequency = 126161280, .index = PLLVAL(141, 3, 3), }, /* FVco 1009.290240 */
34 { .frequency = 132088320, .index = PLLVAL(148, 3, 3), }, /* FVco 1056.706560 */
[all …]
Ds3c2440-pll-12000000.c25 { .frequency = 75000000, .index = PLLVAL(0x75, 3, 3), }, /* FVco 600.000000 */
26 { .frequency = 80000000, .index = PLLVAL(0x98, 4, 3), }, /* FVco 640.000000 */
27 { .frequency = 90000000, .index = PLLVAL(0x70, 2, 3), }, /* FVco 720.000000 */
28 { .frequency = 100000000, .index = PLLVAL(0x5c, 1, 3), }, /* FVco 800.000000 */
29 { .frequency = 110000000, .index = PLLVAL(0x66, 1, 3), }, /* FVco 880.000000 */
30 { .frequency = 120000000, .index = PLLVAL(0x70, 1, 3), }, /* FVco 960.000000 */
31 { .frequency = 150000000, .index = PLLVAL(0x75, 3, 2), }, /* FVco 600.000000 */
32 { .frequency = 160000000, .index = PLLVAL(0x98, 4, 2), }, /* FVco 640.000000 */
33 { .frequency = 170000000, .index = PLLVAL(0x4d, 1, 2), }, /* FVco 680.000000 */
34 { .frequency = 180000000, .index = PLLVAL(0x70, 2, 2), }, /* FVco 720.000000 */
[all …]
/arch/arm/mach-s3c2410/
Dpll.c37 { .frequency = 34000000, .index = PLLVAL(82, 2, 3), },
38 { .frequency = 45000000, .index = PLLVAL(82, 1, 3), },
39 { .frequency = 51000000, .index = PLLVAL(161, 3, 3), },
40 { .frequency = 48000000, .index = PLLVAL(120, 2, 3), },
41 { .frequency = 56000000, .index = PLLVAL(142, 2, 3), },
42 { .frequency = 68000000, .index = PLLVAL(82, 2, 2), },
43 { .frequency = 79000000, .index = PLLVAL(71, 1, 2), },
44 { .frequency = 85000000, .index = PLLVAL(105, 2, 2), },
45 { .frequency = 90000000, .index = PLLVAL(112, 2, 2), },
46 { .frequency = 101000000, .index = PLLVAL(127, 2, 2), },
[all …]
/arch/m68k/sun3x/
Ddvma.c44 #define dvma_entry_paddr(index) (iommu_pte[index] & IOMMU_ADDR_MASK) argument
45 #define dvma_entry_vaddr(index,paddr) ((index << DVMA_PAGE_SHIFT) | \ argument
48 #define dvma_entry_set(index,addr) (iommu_pte[index] = \
52 #define dvma_entry_set(index,addr) (iommu_pte[index] = \ argument
56 #define dvma_entry_clr(index) (iommu_pte[index] = IOMMU_DT_INVALID) argument
68 unsigned long index; in dvma_print() local
70 index = dvma_addr >> DVMA_PAGE_SHIFT; in dvma_print()
72 printk("idx %lx dvma_addr %08lx paddr %08lx\n", index, dvma_addr, in dvma_print()
73 dvma_entry_paddr(index)); in dvma_print()
154 unsigned long end, index; in dvma_map_iommu() local
[all …]
/arch/mips/cavium-octeon/executive/
Dcvmx-helper-sgmii.c45 void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
46 void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
56 static int __cvmx_helper_sgmii_hardware_init_one_time(int interface, int index) in __cvmx_helper_sgmii_hardware_init_one_time() argument
64 gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); in __cvmx_helper_sgmii_hardware_init_one_time()
66 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); in __cvmx_helper_sgmii_hardware_init_one_time()
74 cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); in __cvmx_helper_sgmii_hardware_init_one_time()
76 cvmx_read_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface)); in __cvmx_helper_sgmii_hardware_init_one_time()
86 cvmx_write_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface), in __cvmx_helper_sgmii_hardware_init_one_time()
102 cvmx_read_csr(CVMX_PCSX_ANX_ADV_REG(index, interface)); in __cvmx_helper_sgmii_hardware_init_one_time()
107 cvmx_write_csr(CVMX_PCSX_ANX_ADV_REG(index, interface), in __cvmx_helper_sgmii_hardware_init_one_time()
[all …]
Dcvmx-helper-rgmii.c106 int index = port & 0xf; in cvmx_helper_rgmii_internal_loopback() local
114 cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1); in cvmx_helper_rgmii_internal_loopback()
115 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200); in cvmx_helper_rgmii_internal_loopback()
116 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000); in cvmx_helper_rgmii_internal_loopback()
117 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); in cvmx_helper_rgmii_internal_loopback()
119 cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), (1 << index) | tmp); in cvmx_helper_rgmii_internal_loopback()
121 cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), (1 << index) | tmp); in cvmx_helper_rgmii_internal_loopback()
123 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), (1 << index) | tmp); in cvmx_helper_rgmii_internal_loopback()
125 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); in cvmx_helper_rgmii_internal_loopback()
273 int index = cvmx_helper_get_interface_index_num(ipd_port); in __cvmx_helper_rgmii_link_get() local
[all …]
/arch/m68k/platform/5272/
Dintc.c40 unsigned char index; member
45 /*MCF_IRQ_SPURIOUS*/ { .icr = 0, .index = 0, .ack = 0, },
46 /*MCF_IRQ_EINT1*/ { .icr = MCFSIM_ICR1, .index = 28, .ack = 1, },
47 /*MCF_IRQ_EINT2*/ { .icr = MCFSIM_ICR1, .index = 24, .ack = 1, },
48 /*MCF_IRQ_EINT3*/ { .icr = MCFSIM_ICR1, .index = 20, .ack = 1, },
49 /*MCF_IRQ_EINT4*/ { .icr = MCFSIM_ICR1, .index = 16, .ack = 1, },
50 /*MCF_IRQ_TIMER1*/ { .icr = MCFSIM_ICR1, .index = 12, .ack = 0, },
51 /*MCF_IRQ_TIMER2*/ { .icr = MCFSIM_ICR1, .index = 8, .ack = 0, },
52 /*MCF_IRQ_TIMER3*/ { .icr = MCFSIM_ICR1, .index = 4, .ack = 0, },
53 /*MCF_IRQ_TIMER4*/ { .icr = MCFSIM_ICR1, .index = 0, .ack = 0, },
[all …]
/arch/powerpc/xmon/
Dspu-dis.c57 const struct spu_opcode *index; in get_index_for_opcode() local
65 if ((index = spu_disassemble_table[opcode & 0x780]) != 0 in get_index_for_opcode()
66 && index->insn_type == RRR) in get_index_for_opcode()
67 return index; in get_index_for_opcode()
69 if ((index = spu_disassemble_table[opcode & 0x7f0]) != 0 in get_index_for_opcode()
70 && (index->insn_type == RI18 || index->insn_type == LBT)) in get_index_for_opcode()
71 return index; in get_index_for_opcode()
73 if ((index = spu_disassemble_table[opcode & 0x7f8]) != 0 in get_index_for_opcode()
74 && index->insn_type == RI10) in get_index_for_opcode()
75 return index; in get_index_for_opcode()
[all …]
/arch/ia64/include/asm/
Dintel_intrin.h81 #define __ia64_set_dbr(index, val) \ argument
82 __setIndReg(_IA64_REG_INDR_DBR, index, val)
83 #define ia64_set_ibr(index, val) \ argument
84 __setIndReg(_IA64_REG_INDR_IBR, index, val)
85 #define ia64_set_pkr(index, val) \ argument
86 __setIndReg(_IA64_REG_INDR_PKR, index, val)
87 #define ia64_set_pmc(index, val) \ argument
88 __setIndReg(_IA64_REG_INDR_PMC, index, val)
89 #define ia64_set_pmd(index, val) \ argument
90 __setIndReg(_IA64_REG_INDR_PMD, index, val)
[all …]
Dgcc_intrin.h427 #define __ia64_set_dbr(index, val) \ argument
428 asm volatile ("mov dbr[%0]=%1" :: "r"(index), "r"(val) : "memory")
430 #define ia64_set_ibr(index, val) \ argument
431 asm volatile ("mov ibr[%0]=%1" :: "r"(index), "r"(val) : "memory")
433 #define ia64_set_pkr(index, val) \ argument
434 asm volatile ("mov pkr[%0]=%1" :: "r"(index), "r"(val) : "memory")
436 #define ia64_set_pmc(index, val) \ argument
437 asm volatile ("mov pmc[%0]=%1" :: "r"(index), "r"(val) : "memory")
439 #define ia64_set_pmd(index, val) \ argument
440 asm volatile ("mov pmd[%0]=%1" :: "r"(index), "r"(val) : "memory")
[all …]
/arch/blackfin/mach-common/
Dcpufreq.c25 .index = 0,
29 .index = 1,
33 .index = 2,
37 .index = 0,
61 int index; in bfin_init_tables() local
72 for (index = 0; (cclk >> index) >= min_cclk && csel <= 3; index++, csel++) { in bfin_init_tables()
73 bfin_freq_table[index].frequency = cclk >> index; in bfin_init_tables()
74 dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */ in bfin_init_tables()
75 dpm_state_table[index].tscale = (TIME_SCALE / (1 << csel)) - 1; in bfin_init_tables()
78 bfin_freq_table[index].frequency, in bfin_init_tables()
[all …]
/arch/s390/crypto/
Dsha_common.c25 unsigned int index; in s390_sha_update() local
29 index = ctx->count & (bsize - 1); in s390_sha_update()
32 if ((index + len) < bsize) in s390_sha_update()
36 if (index) { in s390_sha_update()
37 memcpy(ctx->buf + index, data, bsize - index); in s390_sha_update()
40 data += bsize - index; in s390_sha_update()
41 len -= bsize - index; in s390_sha_update()
42 index = 0; in s390_sha_update()
55 memcpy(ctx->buf + index , data, len); in s390_sha_update()
66 unsigned int index, end, plen; in s390_sha_final() local
[all …]
/arch/powerpc/kernel/
Dlegacy_serial.c76 int index; in add_legacy_port() local
88 index = want_index; in add_legacy_port()
90 index = legacy_serial_count; in add_legacy_port()
96 if (index >= MAX_LEGACY_SERIAL_PORTS) in add_legacy_port()
98 if (index >= legacy_serial_count) in add_legacy_port()
99 legacy_serial_count = index + 1; in add_legacy_port()
102 if (legacy_serial_infos[index].np != 0) { in add_legacy_port()
106 index, legacy_serial_count); in add_legacy_port()
108 legacy_serial_ports[index]; in add_legacy_port()
110 legacy_serial_infos[index]; in add_legacy_port()
[all …]
Dptrace32.c111 int index; in compat_arch_ptrace() local
116 index = (unsigned long) addr >> 2; in compat_arch_ptrace()
117 if ((addr & 3) || (index > PT_FPSCR32)) in compat_arch_ptrace()
121 if (index < PT_FPR0) { in compat_arch_ptrace()
122 tmp = ptrace_get_reg(child, index); in compat_arch_ptrace()
131 [FPRINDEX(index)]; in compat_arch_ptrace()
146 u32 index; in compat_arch_ptrace() local
154 index = (u64)addr >> 2; in compat_arch_ptrace()
155 numReg = index / 2; in compat_arch_ptrace()
157 if (index % 2) in compat_arch_ptrace()
[all …]
/arch/ia64/sn/pci/pcibr/
Dpcibr_ate.c24 int index; in mark_ate() local
27 for (index = start; length < number; index++, length++) in mark_ate()
28 ate[index] = value; in mark_ate()
39 int index; in find_free_ate() local
42 for (index = start; index < ate_resource->num_ate;) { in find_free_ate()
43 if (!ate[index]) { in find_free_ate()
47 start_free = index; /* Found start free ate */ in find_free_ate()
53 index = i + 1; in find_free_ate()
60 index++; /* Try next ate */ in find_free_ate()
160 void pcibr_ate_free(struct pcibus_info *pcibus_info, int index) in pcibr_ate_free() argument
[all …]
/arch/alpha/kernel/
Dcore_tsunami.c179 tsunami_pchip *pchip = hose->index ? TSUNAMI_pchip1 : TSUNAMI_pchip0; in tsunami_pci_tbi()
246 tsunami_init_one_pchip(tsunami_pchip *pchip, int index) in tsunami_init_one_pchip() argument
254 if (index == 0) in tsunami_init_one_pchip()
266 = (TSUNAMI_MEM(index) & 0xffffffffffL) | 0x80000000000L; in tsunami_init_one_pchip()
268 = (TSUNAMI_IO(index) & 0xffffffffffL) | 0x80000000000L; in tsunami_init_one_pchip()
270 hose->config_space_base = TSUNAMI_CONF(index); in tsunami_init_one_pchip()
271 hose->index = index; in tsunami_init_one_pchip()
273 hose->io_space->start = TSUNAMI_IO(index) - TSUNAMI_IO_BIAS; in tsunami_init_one_pchip()
275 hose->io_space->name = pci_io_names[index]; in tsunami_init_one_pchip()
278 hose->mem_space->start = TSUNAMI_MEM(index) - TSUNAMI_MEM_BIAS; in tsunami_init_one_pchip()
[all …]
/arch/powerpc/mm/
Dmmu_context_hash64.c41 int index; in __init_new_context() local
49 err = ida_get_new_above(&mmu_context_ida, 1, &index); in __init_new_context()
57 if (index > MAX_CONTEXT) { in __init_new_context()
59 ida_remove(&mmu_context_ida, index); in __init_new_context()
64 return index; in __init_new_context()
70 int index; in init_new_context() local
72 index = __init_new_context(); in init_new_context()
73 if (index < 0) in init_new_context()
74 return index; in init_new_context()
83 mm->context.id = index; in init_new_context()
[all …]
Dfsl_booke_mmu.c109 static void settlbcam(int index, unsigned long virt, phys_addr_t phys, in settlbcam() argument
121 TLBCAM[index].MAS0 = MAS0_TLBSEL(1) | MAS0_ESEL(index) | MAS0_NV(index+1); in settlbcam()
122 TLBCAM[index].MAS1 = MAS1_VALID | MAS1_IPROT | MAS1_TSIZE(tsize) | MAS1_TID(pid); in settlbcam()
123 TLBCAM[index].MAS2 = virt & PAGE_MASK; in settlbcam()
125 TLBCAM[index].MAS2 |= (flags & _PAGE_WRITETHRU) ? MAS2_W : 0; in settlbcam()
126 TLBCAM[index].MAS2 |= (flags & _PAGE_NO_CACHE) ? MAS2_I : 0; in settlbcam()
127 TLBCAM[index].MAS2 |= (flags & _PAGE_COHERENT) ? MAS2_M : 0; in settlbcam()
128 TLBCAM[index].MAS2 |= (flags & _PAGE_GUARDED) ? MAS2_G : 0; in settlbcam()
129 TLBCAM[index].MAS2 |= (flags & _PAGE_ENDIAN) ? MAS2_E : 0; in settlbcam()
131 TLBCAM[index].MAS3 = (phys & MAS3_RPN) | MAS3_SX | MAS3_SR; in settlbcam()
[all …]
/arch/parisc/kernel/
Dftrace.c27 int index; in push_return_trace() local
38 index = ++current->curr_ret_stack; in push_return_trace()
40 current->ret_stack[index].ret = ret; in push_return_trace()
41 current->ret_stack[index].func = func; in push_return_trace()
42 current->ret_stack[index].calltime = time; in push_return_trace()
43 *depth = index; in push_return_trace()
51 int index; in pop_return_trace() local
53 index = current->curr_ret_stack; in pop_return_trace()
55 if (unlikely(index < 0)) { in pop_return_trace()
64 *ret = current->ret_stack[index].ret; in pop_return_trace()
[all …]
/arch/parisc/math-emu/
Ddecode_exc.c69 #define Excp_type(index) Exceptiontype(Fpu_register[index]) argument
70 #define Excp_instr(index) Instructionfield(Fpu_register[index]) argument
71 #define Clear_excp_register(index) Allexception(Fpu_register[index]) = 0 argument
76 #define Fpu_sgl(index) Fpu_register[index*2] argument
78 #define Fpu_dblp1(index) Fpu_register[index*2] argument
79 #define Fpu_dblp2(index) Fpu_register[(index*2)+1] argument
81 #define Fpu_quadp1(index) Fpu_register[index*2] argument
82 #define Fpu_quadp2(index) Fpu_register[(index*2)+1] argument
83 #define Fpu_quadp3(index) Fpu_register[(index*2)+2] argument
84 #define Fpu_quadp4(index) Fpu_register[(index*2)+3] argument
/arch/powerpc/sysdev/
Dmmio_nvram.c37 static ssize_t mmio_nvram_read(char *buf, size_t count, loff_t *index) in mmio_nvram_read() argument
41 if (*index >= mmio_nvram_len) in mmio_nvram_read()
43 if (*index + count > mmio_nvram_len) in mmio_nvram_read()
44 count = mmio_nvram_len - *index; in mmio_nvram_read()
48 memcpy_fromio(buf, mmio_nvram_start + *index, count); in mmio_nvram_read()
52 *index += count; in mmio_nvram_read()
73 static ssize_t mmio_nvram_write(char *buf, size_t count, loff_t *index) in mmio_nvram_write() argument
77 if (*index >= mmio_nvram_len) in mmio_nvram_write()
79 if (*index + count > mmio_nvram_len) in mmio_nvram_write()
80 count = mmio_nvram_len - *index; in mmio_nvram_write()
[all …]
/arch/mips/include/asm/
Dvpe.h30 extern int vpe_notify(int index, struct vpe_notifications *notify);
32 extern void *vpe_get_shared(int index);
33 extern int vpe_getuid(int index);
34 extern int vpe_getgid(int index);
35 extern char *vpe_getcwd(int index);
/arch/powerpc/include/asm/
Dpte-hash64-64k.h52 #define __rpte_to_hidx(r,index) ((pte_val((r).pte) & _PAGE_COMBO) ? \ argument
53 (((r).hidx >> ((index)<<2)) & 0xf) : ((pte_val((r).pte) >> 12) & 0xf))
55 #define __rpte_sub_valid(rpte, index) \ argument
56 (pte_val(rpte.pte) & (_PAGE_HPTE_SUB0 >> (index)))
61 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ argument
67 for (index = 0; va < __end; index++, va += (1L << shift)) { \
68 if (!__split || __rpte_sub_valid(rpte, index)) do { \
/arch/mips/include/asm/octeon/
Dcvmx-cmd-queue.h140 uint64_t index:13; member
354 if (likely(qptr->index + cmd_count < qptr->pool_size_m1)) { in cvmx_cmd_queue_write()
358 ptr += qptr->index; in cvmx_cmd_queue_write()
359 qptr->index += cmd_count; in cvmx_cmd_queue_write()
384 count = qptr->pool_size_m1 - qptr->index; in cvmx_cmd_queue_write()
385 ptr += qptr->index; in cvmx_cmd_queue_write()
396 qptr->index = cmd_count; in cvmx_cmd_queue_write()
452 if (likely(qptr->index + 2 < qptr->pool_size_m1)) { in cvmx_cmd_queue_write2()
456 ptr += qptr->index; in cvmx_cmd_queue_write2()
457 qptr->index += 2; in cvmx_cmd_queue_write2()
[all …]
/arch/powerpc/sysdev/bestcomm/
Dbestcomm.h55 unsigned short index; member
108 return ((tsk->index + 1) == tsk->num_bd) ? 0 : tsk->index + 1; in _bcom_next_index()
129 return tsk->index == tsk->outdex; in bcom_queue_empty()
148 *bcom_get_bd(struct bcom_task *tsk, unsigned int index) in bcom_get_bd() argument
152 return ((void *)tsk->bd) + (index * tsk->bd_size); in bcom_get_bd()
181 bd = bcom_get_bd(tsk, tsk->index); in bcom_prepare_next_buffer()
189 struct bcom_bd *bd = bcom_get_bd(tsk, tsk->index); in bcom_submit_next_buffer()
191 tsk->cookie[tsk->index] = cookie; in bcom_submit_next_buffer()
194 tsk->index = _bcom_next_index(tsk); in bcom_submit_next_buffer()

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