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Searched refs:input_rate (Results 1 – 8 of 8) sorted by relevance

/arch/arm/mach-davinci/
Dclock.h81 u32 input_rate; member
Dclock.c266 rate = pll->input_rate; in clk_sysclk_recalc()
310 input = pll->input_rate; in davinci_set_sysclk_rate()
376 rate = pll->input_rate = clk->parent->rate; in clk_pllclk_recalc()
Dtnetv107x.c684 clk->pll_data->input_rate = ref; in clk_sspll_recalc()
/arch/c6x/include/asm/
Dclock.h112 u32 input_rate; member
/arch/arm/mach-tegra/
Dclock.h63 unsigned long input_rate; member
Dtegra30_clocks.c897 unsigned long input_rate = clk_get_rate(c->parent); in tegra30_pll_clk_init() local
898 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { in tegra30_pll_clk_init()
899 if (sel->input_rate == input_rate && in tegra30_pll_clk_init()
974 unsigned long input_rate; in tegra30_pll_clk_set_rate() local
1000 input_rate = clk_get_rate(c->parent); in tegra30_pll_clk_set_rate()
1003 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { in tegra30_pll_clk_set_rate()
1004 if (sel->input_rate == input_rate && sel->output_rate == rate) { in tegra30_pll_clk_set_rate()
1020 if (sel->input_rate == 0) { in tegra30_pll_clk_set_rate()
1025 switch (input_rate) { in tegra30_pll_clk_set_rate()
1039 __func__, input_rate); in tegra30_pll_clk_set_rate()
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Dtegra2_clocks.c668 unsigned long input_rate; in tegra2_pll_clk_set_rate() local
673 input_rate = clk_get_rate(c->parent); in tegra2_pll_clk_set_rate()
674 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { in tegra2_pll_clk_set_rate()
675 if (sel->input_rate == input_rate && sel->output_rate == rate) { in tegra2_pll_clk_set_rate()
/arch/c6x/platforms/
Dpll.c228 rate = pll->input_rate; in clk_sysclk_recalc()
280 rate = pll->input_rate = clk->parent->rate; in clk_pllclk_recalc()