Searched refs:mfdcr (Results 1 – 9 of 9) sorted by relevance
39 while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC)) in l2c_diag()42 return mfdcr(dcrbase_l2c + DCRN_L2C0_DATA); in l2c_diag()47 u32 sr = mfdcr(dcrbase_l2c + DCRN_L2C0_SR); in l2c_error_handler()130 mfdcr(dcrbase_isram + DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE); in ppc4xx_l2c_probe()132 mfdcr(dcrbase_isram + DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK); in ppc4xx_l2c_probe()134 mfdcr(dcrbase_isram + DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK); in ppc4xx_l2c_probe()136 mfdcr(dcrbase_isram + DCRN_SRAM0_SB2CR) & ~SRAM_SBCR_BU_MASK); in ppc4xx_l2c_probe()138 mfdcr(dcrbase_isram + DCRN_SRAM0_SB3CR) & ~SRAM_SBCR_BU_MASK); in ppc4xx_l2c_probe()141 r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG) & in ppc4xx_l2c_probe()150 while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC)) in ppc4xx_l2c_probe()[all …]
36 mfdcr r3,0; blr42 mfdcr r3,dcr; blr
67 er = mfdcr(uic->dcrbase + UIC_ER); in uic_unmask_irq()81 er = mfdcr(uic->dcrbase + UIC_ER); in uic_mask_irq()107 er = mfdcr(uic->dcrbase + UIC_ER); in uic_mask_ack_irq()155 tr = mfdcr(uic->dcrbase + UIC_TR); in uic_set_irq_type()156 pr = mfdcr(uic->dcrbase + UIC_PR); in uic_set_irq_type()214 msr = mfdcr(uic->dcrbase + UIC_MSR); in uic_irq_cascade()331 msr = mfdcr(primary_uic->dcrbase + UIC_MSR); in uic_get_irq()
110 banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B0BAS)); in ibm440spe_fixup_memsize()113 banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B1BAS)); in ibm440spe_fixup_memsize()116 banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B2BAS)); in ibm440spe_fixup_memsize()119 banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B3BAS)); in ibm440spe_fixup_memsize()301 while (mfdcr(DCRN_MAL0_CFG) & MAL_RESET) in ibm4xx_quiesce_eth()317 bxcr = mfdcr(DCRN_EBC0_CFGDATA); in ibm4xx_fixup_ebc_ranges()337 u32 sys0 = mfdcr(DCRN_CPC0_SYS0); in ibm440gp_fixup_clocks()338 u32 cr0 = mfdcr(DCRN_CPC0_CR0); in ibm440gp_fixup_clocks()554 u32 pllmr = mfdcr(DCRN_CPC0_PLLMR); in ibm405gp_fixup_clocks()555 u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0); in ibm405gp_fixup_clocks()[all …]
4 #define mfdcr(rn) \ macro25 mfdcr(DCRN_SDRAM0_CFGDATA); })178 mfdcr(DCRN_SDR0_CONFIG_DATA); })196 mfdcr(DCRN_CPR0_CFGDATA); })
29 u32 uart = mfdcr(DCRN_CPC0_UCR) & 0x7f; in hotfoot_fixups()
40 #define dcr_read_native(host, dcr_n) mfdcr(dcr_n + host.base)64 #define mfdcr(rn) \ macro
68 mfdcr r3,DCRN_PLB4A0_ACR
75 mfdcr(DCRN_CPR0_CONFIG_DATA)); in kvmppc_core_emulate_op()