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Searched refs:mtctl (Results 1 – 17 of 17) sorted by relevance

/arch/parisc/kernel/
Dhead.S76 mtctl %r4,%cr24 /* Initialize kernel root pointer */
77 mtctl %r4,%cr25 /* Initialize user root pointer */
129 mtctl %r6,%cr30
220 mtctl %r0,%cr8
221 mtctl %r0,%cr9
222 mtctl %r0,%cr12
223 mtctl %r0,%cr13
236 mtctl %r10,%cr11
251 mtctl %r10,%cr14
263 mtctl %r0,%cr17 /* Clear IIASQ tail */
[all …]
Dreal2.S126 # define POP_CR(r, where) LDREG,mb -REG_SZ(where), %r1 ! mtctl %r1, r
173 mtctl %r0, %cr17 /* Clear IIASQ tail */
174 mtctl %r0, %cr17 /* Clear IIASQ head */
175 mtctl %r1, %cr18 /* IIAOQ head */
177 mtctl %r1, %cr18 /* IIAOQ tail */
179 mtctl %r1, %cr22
207 mtctl %r0, %cr17 /* Clear IIASQ tail */
208 mtctl %r0, %cr17 /* Clear IIASQ head */
209 mtctl %r1, %cr18 /* IIAOQ head */
211 mtctl %r1, %cr18 /* IIAOQ tail */
[all …]
Dhpmc.S135 mtctl %r4,ipsw
136 mtctl %r0,pcsq
137 mtctl %r0,pcsq
139 mtctl %r4,pcoq
141 mtctl %r4,pcoq
244 mtctl %r4,%cr24 /* Initialize kernel root pointer */
245 mtctl %r4,%cr25 /* Initialize user root pointer */
Dtime.c109 mtctl(next_tick, 16); in timer_interrupt()
123 mtctl(next_tick+cpt, 16); in timer_interrupt()
229 mtctl(next_tick, 16); /* kick off Interval Timer (CR16) */ in start_cpu_itimer()
Dpacache.S66 mtctl %r0, %cr17 /* Clear IIASQ tail */
67 mtctl %r0, %cr17 /* Clear IIASQ head */
68 mtctl %r1, %cr18 /* IIAOQ head */
70 mtctl %r1, %cr18 /* IIAOQ tail */
72 mtctl %r1, %ipsw
177 mtctl %r0, %cr17 /* Clear IIASQ tail */
178 mtctl %r0, %cr17 /* Clear IIASQ head */
179 mtctl %r1, %cr18 /* IIAOQ head */
181 mtctl %r1, %cr18 /* IIAOQ tail */
184 mtctl %r1, %ipsw /* restore I-bit (entire PSW) */
[all …]
Dirq.c95 mtctl(mask, 23); in cpu_ack_irq()
412 mtctl(~0UL, 23); /* EIRR : clear all pending external intr */ in init_IRQ()
Dperf_asm.S56 mtctl %r26,ccr ; turn on performance coprocessor
61 mtctl %r26,ccr ; turn off performance coprocessor
82 mtctl %r26,ccr ; turn on performance coprocessor
87 mtctl %r26,ccr ; turn off performance coprocessor
Dentry.S77 mtctl %r0, %cr17 /* Clear IIASQ tail */
78 mtctl %r0, %cr17 /* Clear IIASQ head */
79 mtctl %r1, %ipsw
81 mtctl %r1, %cr18 /* Set IIAOQ tail */
83 mtctl %r1, %cr18 /* Set IIAOQ head */
839 mtctl %r25,%cr30
842 mtctl %r0, %cr0 /* Needed for single stepping */
1387 mtctl %r8,%ipsw
1805 mtctl %r3, %cr27
2126 mtctl %r2,%cr0 /* for immediate trap */
Dsetup.c383 mtctl(coproc_cfg.ccr_functional, 10); in start_parisc()
Dprocessor.c311 mtctl(coproc_cfg.ccr_functional, 10); /* 10 == Coprocessor Control Reg */ in init_per_cpu()
Dsignal.c401 mtctl(-1, 0); in setup_rt_frame()
Dsyscall.S70 mtctl %r26, %cr27 /* move arg0 to the control register */
/arch/parisc/include/asm/
Dspecial_insns.h13 #define mtctl(gr, cr) \ macro
23 mtctl(val, 15); in set_eiem()
Dmmu_context.h49 mtctl(__space_to_prot(context), 8); in load_context()
56 mtctl(__pa(next->pgd), 25); in switch_mm()
Dassembly.h178 #define REST_CR(r, where) LDREG where, %r1 ! mtctl %r1, r
383 mtctl %r3, %cr27
427 mtctl %r3, %cr27
444 mtctl %r0, %cr17
448 mtctl %r0, %cr18
/arch/parisc/hpux/
Dgate.S40 mtctl %r30,%cr28
Dwrappers.S95 mtctl %r25,%cr29