| /arch/arm/mach-omap2/ |
| D | clkt2xxx_dpllcore.c | 108 u32 cur_rate, low, mult, div, valid_rate, done_rate; in omap2_reprogram_dpllcore() local
114 mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); in omap2_reprogram_dpllcore()
115 mult &= OMAP24XX_CORE_CLK_SRC_MASK; in omap2_reprogram_dpllcore()
117 if ((rate == (cur_rate / 2)) && (mult == 2)) { in omap2_reprogram_dpllcore()
119 } else if ((rate == (cur_rate * 2)) && (mult == 1)) { in omap2_reprogram_dpllcore()
126 if (mult == 1) in omap2_reprogram_dpllcore()
143 mult = ((rate / 2) / 1000000); in omap2_reprogram_dpllcore()
147 mult = (rate / 1000000); in omap2_reprogram_dpllcore()
151 tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask)); in omap2_reprogram_dpllcore()
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| /arch/arm/kernel/ |
| D | sched_clock.c | 22 u32 mult; member
32 .mult = NSEC_PER_SEC / HZ,
44 static inline u64 cyc_to_ns(u64 cyc, u32 mult, u32 shift) in cyc_to_ns() argument
46 return (cyc * mult) >> shift; in cyc_to_ns()
71 return epoch_ns + cyc_to_ns((cyc - epoch_cyc) & mask, cd.mult, cd.shift); in cyc_to_sched_clock()
86 cd.mult, cd.shift); in update_sched_clock()
126 clocks_calc_mult_shift(&cd.mult, &cd.shift, rate, NSEC_PER_SEC, 0); in setup_sched_clock()
139 wrap = cyc_to_ns((1ULL << bits) - 1, cd.mult, cd.shift); in setup_sched_clock()
144 res = cyc_to_ns(1ULL, cd.mult, cd.shift); in setup_sched_clock()
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| /arch/mn10300/include/asm/ |
| D | div64.h | 79 unsigned __muldiv64u(unsigned val, unsigned mult, unsigned div) in __muldiv64u() argument
87 : "0"(val), "ir"(mult), "r"(div) in __muldiv64u()
100 signed __muldiv64s(signed val, signed mult, signed div) in __muldiv64s() argument
108 : "0"(val), "ir"(mult), "r"(div) in __muldiv64s()
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| /arch/x86/math-emu/ |
| D | poly.h | 34 asmlinkage void mul32_Xsig(Xsig *, const unsigned long mult);
35 asmlinkage void mul64_Xsig(Xsig *, const unsigned long long *mult);
36 asmlinkage void mul_Xsig_Xsig(Xsig *dest, const Xsig *mult);
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| /arch/mips/cavium-octeon/ |
| D | csrc-octeon.c | 87 u64 mult = clocksource_mips.mult; in sched_clock() local
101 : [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift) in sched_clock()
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| /arch/arm/mach-davinci/ |
| D | clock.c | 370 u32 ctrl, mult = 1, prediv = 1, postdiv = 1; in clk_pllclk_recalc() local
380 mult = __raw_readl(pll->base + PLLM); in clk_pllclk_recalc()
382 mult = 2 * (mult & PLLM_PLLM_MASK); in clk_pllclk_recalc()
384 mult = (mult & PLLM_PLLM_MASK) + 1; in clk_pllclk_recalc()
410 rate *= mult; in clk_pllclk_recalc()
420 if (mult > 1) in clk_pllclk_recalc()
421 pr_debug("* %d ", mult); in clk_pllclk_recalc()
440 unsigned int mult, unsigned int postdiv) in davinci_set_pllrate() argument
462 if (mult) in davinci_set_pllrate()
463 mult = mult - 1; in davinci_set_pllrate()
[all …]
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| D | da850.c | 813 unsigned int mult; member
822 .mult = 19,
831 .mult = 17,
840 .mult = 31,
849 .mult = 25,
858 .mult = 25,
867 .mult = 20,
991 unsigned int prediv, mult, postdiv; in da850_set_pll0rate() local
998 mult = opp->mult; in da850_set_pll0rate()
1001 ret = davinci_set_pllrate(pll, prediv, mult, postdiv); in da850_set_pll0rate()
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| /arch/sh/kernel/cpu/sh4a/ |
| D | clock-sh7722.c | 57 unsigned long mult; in dll_recalc() local
60 mult = __raw_readl(DLLFRQ); in dll_recalc()
62 mult = 0; in dll_recalc()
64 return clk->parent->rate * mult; in dll_recalc()
79 unsigned long mult = 1; in pll_recalc() local
83 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); in pll_recalc()
87 return (clk->parent->rate * mult) / div; in pll_recalc()
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| D | clock-sh7366.c | 54 unsigned long mult; in dll_recalc() local
57 mult = __raw_readl(DLLFRQ); in dll_recalc()
59 mult = 0; in dll_recalc()
61 return clk->parent->rate * mult; in dll_recalc()
76 unsigned long mult = 1; in pll_recalc() local
80 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); in pll_recalc()
84 return (clk->parent->rate * mult) / div; in pll_recalc()
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| D | clock-sh7723.c | 58 unsigned long mult; in dll_recalc() local
61 mult = __raw_readl(DLLFRQ); in dll_recalc()
63 mult = 0; in dll_recalc()
65 return clk->parent->rate * mult; in dll_recalc()
80 unsigned long mult = 1; in pll_recalc() local
84 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); in pll_recalc()
88 return (clk->parent->rate * mult) / div; in pll_recalc()
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| D | clock-sh7343.c | 54 unsigned long mult; in dll_recalc() local
57 mult = __raw_readl(DLLFRQ); in dll_recalc()
59 mult = 0; in dll_recalc()
61 return clk->parent->rate * mult; in dll_recalc()
76 unsigned long mult = 1; in pll_recalc() local
79 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); in pll_recalc()
81 return clk->parent->rate * mult; in pll_recalc()
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| D | clock-sh7724.c | 61 unsigned long mult = 0; in fll_recalc() local
65 mult = __raw_readl(FLLFRQ) & 0x3ff; in fll_recalc()
70 return (clk->parent->rate * mult) / div; in fll_recalc()
85 unsigned long mult = 1; in pll_recalc() local
88 mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2; in pll_recalc()
90 return clk->parent->rate * mult; in pll_recalc()
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| /arch/c6x/platforms/ |
| D | pll.c | 271 u32 ctrl, mult = 0, prediv = 0, postdiv = 0; in clk_pllclk_recalc() local
288 mult = pll_read(pll, PLLM); in clk_pllclk_recalc()
289 mult = (mult & PLLM_PLLM_MASK) + 1; in clk_pllclk_recalc()
309 if (mult) in clk_pllclk_recalc()
310 rate *= mult; in clk_pllclk_recalc()
317 prediv, mult, postdiv, rate / 1000000); in clk_pllclk_recalc()
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| /arch/arm/plat-samsung/include/plat/ |
| D | hwmon.h | 28 unsigned int mult; member
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| /arch/arm/mach-goldfish/ |
| D | timer.c | 107 .mult = 1,
118 .mult = 1,
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| /arch/blackfin/kernel/ |
| D | time-ts.c | 49 bfin_cs_cycles.mult, bfin_cs_cycles.shift); in bfin_cs_cycles_sched_clock()
93 bfin_cs_gptimer0.mult, bfin_cs_gptimer0.shift); in bfin_cs_gptimer0_sched_clock()
210 evt->mult = div_sc(clock_tick, NSEC_PER_SEC, evt->shift); in bfin_gptmr0_clockevent_init()
324 evt->mult = div_sc(clock_tick, NSEC_PER_SEC, evt->shift); in bfin_coretmr_clockevent_init()
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| /arch/x86/include/asm/ |
| D | vgtod.h | 14 u32 mult; member
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| /arch/arm/mach-shmobile/ |
| D | clock-sh7377.c | 105 unsigned long mult = 1; in pllc1_recalc() local
108 mult = (((__raw_readl(RTFRQCR) >> 24) & 0x3f) + 1) * 2; in pllc1_recalc()
110 return clk->parent->rate * mult; in pllc1_recalc()
132 unsigned long mult = 1; in pllc2_recalc() local
135 mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2; in pllc2_recalc()
137 return clk->parent->rate * mult; in pllc2_recalc()
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| D | clock-sh7367.c | 96 unsigned long mult = 1; in pllc1_recalc() local
99 mult = (((__raw_readl(RTFRQCR) >> 24) & 0x3f) + 1) * 2; in pllc1_recalc()
101 return clk->parent->rate * mult; in pllc1_recalc()
123 unsigned long mult = 1; in pllc2_recalc() local
126 mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2; in pllc2_recalc()
128 return clk->parent->rate * mult; in pllc2_recalc()
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| D | clock-r8a7740.c | 151 unsigned long mult = 1; in pllc01_recalc() local
154 mult = ((__raw_readl(clk->enable_reg) >> 24) & 0x7f) + 1; in pllc01_recalc()
156 return clk->parent->rate * mult; in pllc01_recalc()
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| /arch/microblaze/kernel/ |
| D | timer.c | 172 clockevent_microblaze_timer.mult = in microblaze_clockevent_init()
206 microblaze_cc.mult = div_sc(timer_clock_freq, NSEC_PER_SEC, in init_microblaze_timecounter()
303 return clocksource_cyc2ns(cyc, cs->mult, cs->shift); in sched_clock()
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| /arch/sh/kernel/ |
| D | localtimer.c | 56 clk->mult = 1; in local_timer_setup()
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| /arch/x86/kernel/ |
| D | vsyscall_64.c | 84 struct clocksource *clock, u32 mult) in update_vsyscall() argument
94 vsyscall_gtod_data.clock.mult = mult; in update_vsyscall()
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| /arch/arm/mach-s3c24xx/ |
| D | mach-bast.c | 531 .mult = 3300,
537 .mult = 3300,
543 .mult = 3300,
549 .mult = 3300,
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| /arch/score/kernel/ |
| D | time.c | 91 score_clockevent.mult = div_sc(SYSTEM_CLOCK, NSEC_PER_SEC, in time_init()
|