| /arch/x86/boot/compressed/ |
| D | mkpiggy.c | 38 unsigned long offs; in main() local
73 offs = (olen > ilen) ? olen - ilen : 0; in main()
74 offs += olen >> 12; /* Add 8 bytes for each 32K block */ in main()
75 offs += 64*1024 + 128; /* Add 64K + 128 bytes slack */ in main()
76 offs = (offs+4095) & ~4095; /* Round to a 4K boundary */ in main()
84 printf("z_extract_offset = 0x%lx\n", offs); in main()
87 printf("z_extract_offset_negative = -0x%lx\n", offs); in main()
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| /arch/s390/mm/ |
| D | maccess.c | 123 int offs = 0, size, rc; in copy_to_user_real() local
130 while (offs < count) { in copy_to_user_real()
131 size = min(PAGE_SIZE, count - offs); in copy_to_user_real()
132 if (memcpy_real(buf, src + offs, size)) in copy_to_user_real()
134 if (copy_to_user(dest + offs, buf, size)) in copy_to_user_real()
136 offs += size; in copy_to_user_real()
149 int offs = 0, size, rc; in copy_from_user_real() local
156 while (offs < count) { in copy_from_user_real()
157 size = min(PAGE_SIZE, count - offs); in copy_from_user_real()
158 if (copy_from_user(buf, src + offs, size)) in copy_from_user_real()
[all …]
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| /arch/arm/plat-s5p/ |
| D | irq-eint.c | 64 int offs = EINT_OFFSET(data->irq); in s5p_irq_eint_set_type() local
95 shift = (offs & 0x7) * 4; in s5p_irq_eint_set_type()
103 if ((0 <= offs) && (offs < 8)) in s5p_irq_eint_set_type()
104 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE); in s5p_irq_eint_set_type()
106 else if ((8 <= offs) && (offs < 16)) in s5p_irq_eint_set_type()
107 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE); in s5p_irq_eint_set_type()
109 else if ((16 <= offs) && (offs < 24)) in s5p_irq_eint_set_type()
110 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE); in s5p_irq_eint_set_type()
112 else if ((24 <= offs) && (offs < 32)) in s5p_irq_eint_set_type()
113 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE); in s5p_irq_eint_set_type()
[all …]
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| /arch/arm/mach-s3c2412/ |
| D | gpio.c | 32 unsigned long offs = pin - chip->chip.base; in s3c2412_gpio_set_sleepcfg() local
36 offs *= 2; in s3c2412_gpio_set_sleepcfg()
52 slpcon &= ~(3 << offs); in s3c2412_gpio_set_sleepcfg()
53 slpcon |= state << offs; in s3c2412_gpio_set_sleepcfg()
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| /arch/sparc/kernel/ |
| D | pmc.c | 35 #define pmc_readb(offs) (sbus_readb(regs+offs)) argument
36 #define pmc_writeb(val, offs) (sbus_writeb(val, regs+offs)) argument
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| D | apc.c | 36 #define apc_readb(offs) (sbus_readb(regs+offs)) argument
37 #define apc_writeb(val, offs) (sbus_writeb(val, regs+offs)) argument
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| /arch/arm/plat-omap/include/plat/ |
| D | iommu2.h | 86 static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs) in iommu_read_reg() argument
88 return __raw_readl(obj->regbase + offs); in iommu_read_reg()
91 static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs) in iommu_write_reg() argument
93 __raw_writel(val, obj->regbase + offs); in iommu_write_reg()
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| /arch/arm/mach-s3c64xx/ |
| D | common.c | 232 int offs = eint_offset(data->irq); in s3c_irq_eint_set_type() local
239 if (offs > 27) in s3c_irq_eint_set_type()
242 if (offs <= 15) in s3c_irq_eint_set_type()
277 if (offs <= 15) in s3c_irq_eint_set_type()
278 shift = (offs / 2) * 4; in s3c_irq_eint_set_type()
280 shift = ((offs - 16) / 2) * 4; in s3c_irq_eint_set_type()
290 if (offs < 16) { in s3c_irq_eint_set_type()
291 pin = S3C64XX_GPN(offs); in s3c_irq_eint_set_type()
293 } else if (offs < 23) { in s3c_irq_eint_set_type()
294 pin = S3C64XX_GPL(offs + 8 - 16); in s3c_irq_eint_set_type()
[all …]
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| /arch/arm/plat-samsung/include/plat/ |
| D | gpio-cfg.h | 57 samsung_gpio_pull_t (*get_pull)(struct samsung_gpio_chip *chip, unsigned offs);
58 int (*set_pull)(struct samsung_gpio_chip *chip, unsigned offs,
61 unsigned (*get_config)(struct samsung_gpio_chip *chip, unsigned offs);
62 int (*set_config)(struct samsung_gpio_chip *chip, unsigned offs,
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| /arch/cris/include/arch-v32/arch/hwregs/iop/asm/ |
| D | iop_version_defs_asm.h | 45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs) argument
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ argument
53 ((inst) + offs + (index) * stride)
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| D | iop_scrc_in_defs_asm.h | 45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs) argument
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ argument
53 ((inst) + offs + (index) * stride)
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| D | iop_scrc_out_defs_asm.h | 45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs) argument
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ argument
53 ((inst) + offs + (index) * stride)
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| D | iop_fifo_in_extra_defs_asm.h | 45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs) argument
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ argument
53 ((inst) + offs + (index) * stride)
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| D | iop_fifo_out_extra_defs_asm.h | 45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs) argument
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ argument
53 ((inst) + offs + (index) * stride)
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| D | iop_trigger_grp_defs_asm.h | 45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs) argument
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ argument
53 ((inst) + offs + (index) * stride)
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| /arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/ |
| D | iop_version_defs_asm.h | 42 #define REG_ADDR_X_( inst, offs ) ((inst) + offs) argument
49 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ argument
50 ((inst) + offs + (index) * stride)
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| D | iop_sap_in_defs_asm.h | 42 #define REG_ADDR_X_( inst, offs ) ((inst) + offs) argument
49 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ argument
50 ((inst) + offs + (index) * stride)
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| /arch/cris/include/arch-v32/arch/hwregs/asm/ |
| D | irq_nmi_defs_asm.h | 45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs) argument
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ argument
53 ((inst) + offs + (index) * stride)
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| D | strcop_defs_asm.h | 45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs) argument
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ argument
53 ((inst) + offs + (index) * stride)
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| D | cris_defs_asm.h | 45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs) argument
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ argument
53 ((inst) + offs + (index) * stride)
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| D | strmux_defs_asm.h | 45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs) argument
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ argument
53 ((inst) + offs + (index) * stride)
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| D | config_defs_asm.h | 45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs) argument
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ argument
53 ((inst) + offs + (index) * stride)
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| D | rt_trace_defs_asm.h | 45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs) argument
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ argument
53 ((inst) + offs + (index) * stride)
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| /arch/powerpc/kernel/ |
| D | kvm_emul.S | 40 #define LL64(reg, offs, reg2) ld reg, (offs)(reg2) argument
41 #define STL64(reg, offs, reg2) std reg, (offs)(reg2) argument
43 #define LL64(reg, offs, reg2) lwz reg, (offs + 4)(reg2) argument
44 #define STL64(reg, offs, reg2) stw reg, (offs + 4)(reg2) argument
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| /arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/ |
| D | config_defs_asm.h | 45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs) argument
52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ argument
53 ((inst) + offs + (index) * stride)
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