| /arch/sh/boards/mach-microdev/ |
| D | io.c | 57 void __iomem *microdev_ioport_map(unsigned long offset, unsigned int len) in microdev_ioport_map() argument
61 if ((offset >= IO_LAN91C111_BASE) && in microdev_ioport_map()
62 (offset < IO_LAN91C111_BASE + IO_LAN91C111_EXTENT)) { in microdev_ioport_map()
66 result = IO_LAN91C111_PHYS + offset - IO_LAN91C111_BASE; in microdev_ioport_map()
67 } else if ((offset >= IO_SUPERIO_BASE) && in microdev_ioport_map()
68 (offset < IO_SUPERIO_BASE + IO_SUPERIO_EXTENT)) { in microdev_ioport_map()
74 result = IO_SUPERIO_PHYS + (offset << 1); in microdev_ioport_map()
75 } else if (((offset >= IO_IDE1_BASE) && in microdev_ioport_map()
76 (offset < IO_IDE1_BASE + IO_IDE_EXTENT)) || in microdev_ioport_map()
77 (offset == IO_IDE1_MISC)) { in microdev_ioport_map()
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| /arch/mips/include/asm/octeon/ |
| D | cvmx-pexp-defs.h | 31 #define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31… argument
43 #define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7)… argument
44 #define CVMX_PEXP_NPEI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) … argument
45 #define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset)… argument
46 #define CVMX_PEXP_NPEI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) … argument
68 #define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset… argument
92 #define CVMX_PEXP_NPEI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) … argument
93 #define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F000000A800ull) + ((offset)… argument
94 #define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + ((o… argument
95 #define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F000000B000ull) + ((of… argument
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| D | cvmx-asm.h | 93 #define CVMX_PREPARE_FOR_STORE(address, offset) \ argument
94 asm volatile ("pref 30, " CVMX_TMP_STR(offset) "(%[rbase])" : : \
101 #define CVMX_DONT_WRITE_BACK(address, offset) \ argument
102 asm volatile ("pref 29, " CVMX_TMP_STR(offset) "(%[rbase])" : : \
117 #define CVMX_CACHE(op, address, offset) \ argument
118 asm volatile ("cache " CVMX_TMP_STR(op) ", " CVMX_TMP_STR(offset) "(%[rbase])" \
121 #define CVMX_CACHE_LCKL2(address, offset) CVMX_CACHE(31, address, offset) argument
123 #define CVMX_CACHE_WBIL2(address, offset) CVMX_CACHE(23, address, offset) argument
125 #define CVMX_CACHE_WBIL2I(address, offset) CVMX_CACHE(3, address, offset) argument
127 #define CVMX_CACHE_LTGL2I(address, offset) CVMX_CACHE(7, address, offset) argument
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| /arch/arm/kernel/ |
| D | insn.c | 10 long offset; in __arm_gen_branch_thumb2() local
12 offset = (long)addr - (long)(pc + 4); in __arm_gen_branch_thumb2()
13 if (offset < -16777216 || offset > 16777214) { in __arm_gen_branch_thumb2()
18 s = (offset >> 24) & 0x1; in __arm_gen_branch_thumb2()
19 i1 = (offset >> 23) & 0x1; in __arm_gen_branch_thumb2()
20 i2 = (offset >> 22) & 0x1; in __arm_gen_branch_thumb2()
21 imm10 = (offset >> 12) & 0x3ff; in __arm_gen_branch_thumb2()
22 imm11 = (offset >> 1) & 0x7ff; in __arm_gen_branch_thumb2()
39 long offset; in __arm_gen_branch_arm() local
44 offset = (long)addr - (long)(pc + 8); in __arm_gen_branch_arm()
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| D | module.c | 62 s32 offset; in apply_relocate() local
67 offset = ELF32_R_SYM(rel->r_info); in apply_relocate()
68 if (offset < 0 || offset > (symsec->sh_size / sizeof(Elf32_Sym))) { in apply_relocate()
74 sym = ((Elf32_Sym *)symsec->sh_addr) + offset; in apply_relocate()
98 offset = (*(u32 *)loc & 0x00ffffff) << 2; in apply_relocate()
99 if (offset & 0x02000000) in apply_relocate()
100 offset -= 0x04000000; in apply_relocate()
102 offset += sym->st_value - loc; in apply_relocate()
103 if (offset & 3 || in apply_relocate()
104 offset <= (s32)0xfe000000 || in apply_relocate()
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| /arch/sparc/lib/ |
| D | bitext.c | 29 int offset, count; /* siamese twins */ in bit_map_string_get() local
54 offset = t->first_free; in bit_map_string_get()
56 offset = t->last_off & ~align1; in bit_map_string_get()
59 off_new = find_next_zero_bit(t->map, t->size, offset); in bit_map_string_get()
61 count += off_new - offset; in bit_map_string_get()
62 offset = off_new; in bit_map_string_get()
63 if (offset >= t->size) in bit_map_string_get()
64 offset = 0; in bit_map_string_get()
69 t->size, t->used, offset, len, align, count); in bit_map_string_get()
73 if (offset + len > t->size) { in bit_map_string_get()
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| D | blockops.S | 12 #define BLAST_BLOCK(buf, offset) \ argument
13 std %g0, [buf + offset + 0x38]; \
14 std %g0, [buf + offset + 0x30]; \
15 std %g0, [buf + offset + 0x28]; \
16 std %g0, [buf + offset + 0x20]; \
17 std %g0, [buf + offset + 0x18]; \
18 std %g0, [buf + offset + 0x10]; \
19 std %g0, [buf + offset + 0x08]; \
20 std %g0, [buf + offset + 0x00];
25 #define MIRROR_BLOCK(dst, src, offset, t0, t1, t2, t3, t4, t5, t6, t7) \ argument
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| /arch/ia64/include/asm/uv/ |
| D | uv_hub.h | 172 static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) in uv_pnode_offset_to_vaddr() argument
174 return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset); in uv_pnode_offset_to_vaddr()
183 unsigned long offset) in uv_global_mmr32_address() argument
186 UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset); in uv_global_mmr32_address()
189 static inline void uv_write_global_mmr32(int pnode, unsigned long offset, in uv_write_global_mmr32() argument
192 *uv_global_mmr32_address(pnode, offset) = val; in uv_write_global_mmr32()
196 unsigned long offset) in uv_read_global_mmr32() argument
198 return *uv_global_mmr32_address(pnode, offset); in uv_read_global_mmr32()
206 unsigned long offset) in uv_global_mmr64_address() argument
209 UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset); in uv_global_mmr64_address()
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| /arch/x86/kernel/cpu/ |
| D | perf_event_amd_ibs.c | 90 static inline int get_eilvt(int offset) in get_eilvt() argument
92 return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1); in get_eilvt()
95 static inline int put_eilvt(int offset) in put_eilvt() argument
97 return !setup_APIC_eilvt(offset, 0, 0, 1); in put_eilvt()
105 int offset; in ibs_eilvt_valid() local
112 offset = val & IBSCTL_LVT_OFFSET_MASK; in ibs_eilvt_valid()
116 smp_processor_id(), offset, MSR_AMD64_IBSCTL, val); in ibs_eilvt_valid()
120 if (!get_eilvt(offset)) { in ibs_eilvt_valid()
122 smp_processor_id(), offset, MSR_AMD64_IBSCTL, val); in ibs_eilvt_valid()
177 int offset; in force_ibs_eilvt_setup() local
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| /arch/powerpc/platforms/cell/spufs/ |
| D | spu_restore.c | 83 unsigned int offset; in restore_decr() local
92 offset = LSCSA_QW_OFFSET(decr_status); in restore_decr()
93 decr_running = regs_spill[offset].slot[0] & SPU_DECR_STATUS_RUNNING; in restore_decr()
95 offset = LSCSA_QW_OFFSET(decr); in restore_decr()
96 decr = regs_spill[offset].slot[0]; in restore_decr()
103 unsigned int offset; in write_ppu_mb() local
110 offset = LSCSA_QW_OFFSET(ppu_mb); in write_ppu_mb()
111 data = regs_spill[offset].slot[0]; in write_ppu_mb()
117 unsigned int offset; in write_ppuint_mb() local
124 offset = LSCSA_QW_OFFSET(ppuint_mb); in write_ppuint_mb()
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| D | spu_save.c | 41 unsigned int offset; in save_event_mask() local
46 offset = LSCSA_QW_OFFSET(event_mask); in save_event_mask()
47 regs_spill[offset].slot[0] = spu_readch(SPU_RdEventMask); in save_event_mask()
52 unsigned int offset; in save_tag_mask() local
57 offset = LSCSA_QW_OFFSET(tag_mask); in save_tag_mask()
58 regs_spill[offset].slot[0] = spu_readch(MFC_RdTagMask); in save_tag_mask()
84 unsigned int offset; in save_fpcr() local
90 offset = LSCSA_QW_OFFSET(fpcr); in save_fpcr()
91 regs_spill[offset].v = spu_mffpscr(); in save_fpcr()
96 unsigned int offset; in save_decr() local
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| /arch/mips/alchemy/common/ |
| D | gpiolib.c | 41 static int gpio2_get(struct gpio_chip *chip, unsigned offset) in gpio2_get() argument
43 return alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE); in gpio2_get()
46 static void gpio2_set(struct gpio_chip *chip, unsigned offset, int value) in gpio2_set() argument
48 alchemy_gpio2_set_value(offset + ALCHEMY_GPIO2_BASE, value); in gpio2_set()
51 static int gpio2_direction_input(struct gpio_chip *chip, unsigned offset) in gpio2_direction_input() argument
53 return alchemy_gpio2_direction_input(offset + ALCHEMY_GPIO2_BASE); in gpio2_direction_input()
56 static int gpio2_direction_output(struct gpio_chip *chip, unsigned offset, in gpio2_direction_output() argument
59 return alchemy_gpio2_direction_output(offset + ALCHEMY_GPIO2_BASE, in gpio2_direction_output()
63 static int gpio2_to_irq(struct gpio_chip *chip, unsigned offset) in gpio2_to_irq() argument
65 return alchemy_gpio2_to_irq(offset + ALCHEMY_GPIO2_BASE); in gpio2_to_irq()
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| /arch/m68k/platform/coldfire/ |
| D | gpio.c | 26 int mcf_gpio_direction_input(struct gpio_chip *chip, unsigned offset) in mcf_gpio_direction_input() argument
34 dir &= ~mcfgpio_bit(chip->base + offset); in mcf_gpio_direction_input()
41 int mcf_gpio_get_value(struct gpio_chip *chip, unsigned offset) in mcf_gpio_get_value() argument
45 return mcfgpio_read(mcf_chip->ppdr) & mcfgpio_bit(chip->base + offset); in mcf_gpio_get_value()
48 int mcf_gpio_direction_output(struct gpio_chip *chip, unsigned offset, in mcf_gpio_direction_output() argument
59 data |= mcfgpio_bit(chip->base + offset); in mcf_gpio_direction_output()
61 data &= ~mcfgpio_bit(chip->base + offset); in mcf_gpio_direction_output()
66 data |= mcfgpio_bit(chip->base + offset); in mcf_gpio_direction_output()
73 void mcf_gpio_set_value(struct gpio_chip *chip, unsigned offset, int value) in mcf_gpio_set_value() argument
83 data |= mcfgpio_bit(chip->base + offset); in mcf_gpio_set_value()
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| /arch/m68k/include/asm/ |
| D | mac_psc.h | 222 static inline void psc_write_byte(int offset, __u8 data) in psc_write_byte() argument
224 *((volatile __u8 *)(psc + offset)) = data; in psc_write_byte()
227 static inline void psc_write_word(int offset, __u16 data) in psc_write_word() argument
229 *((volatile __u16 *)(psc + offset)) = data; in psc_write_word()
232 static inline void psc_write_long(int offset, __u32 data) in psc_write_long() argument
234 *((volatile __u32 *)(psc + offset)) = data; in psc_write_long()
237 static inline u8 psc_read_byte(int offset) in psc_read_byte() argument
239 return *((volatile __u8 *)(psc + offset)); in psc_read_byte()
242 static inline u16 psc_read_word(int offset) in psc_read_word() argument
244 return *((volatile __u16 *)(psc + offset)); in psc_read_word()
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| /arch/arm/mach-vt8500/ |
| D | gpio.c | 43 unsigned offset) in vt8500_muxed_gpio_request() argument
48 val |= (1 << vt8500_chip->shift << offset); in vt8500_muxed_gpio_request()
55 unsigned offset) in vt8500_muxed_gpio_free() argument
60 val &= ~(1 << vt8500_chip->shift << offset); in vt8500_muxed_gpio_free()
65 unsigned offset) in vt8500_muxed_gpio_direction_input() argument
70 val &= ~(1 << vt8500_chip->shift << offset); in vt8500_muxed_gpio_direction_input()
77 unsigned offset, int value) in vt8500_muxed_gpio_direction_output() argument
82 val |= (1 << vt8500_chip->shift << offset); in vt8500_muxed_gpio_direction_output()
87 val |= (1 << vt8500_chip->shift << offset); in vt8500_muxed_gpio_direction_output()
94 unsigned offset) in vt8500_muxed_gpio_get_value() argument
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| /arch/arm/boot/compressed/ |
| D | atags_to_fdt.c | 6 int offset = fdt_path_offset(fdt, node_path); in node_offset() local
7 if (offset == -FDT_ERR_NOTFOUND) in node_offset()
8 offset = fdt_add_subnode(fdt, 0, node_path); in node_offset()
9 return offset; in node_offset()
15 int offset = node_offset(fdt, node_path); in setprop() local
16 if (offset < 0) in setprop()
17 return offset; in setprop()
18 return fdt_setprop(fdt, offset, property, val_array, size); in setprop()
24 int offset = node_offset(fdt, node_path); in setprop_string() local
25 if (offset < 0) in setprop_string()
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| /arch/x86/include/asm/uv/ |
| D | uv_hub.h | 132 unsigned long offset; member
355 static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) in uv_pnode_offset_to_vaddr() argument
357 return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset); in uv_pnode_offset_to_vaddr()
384 static inline unsigned long *uv_global_mmr32_address(int pnode, unsigned long offset) in uv_global_mmr32_address() argument
387 UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset); in uv_global_mmr32_address()
390 static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val) in uv_write_global_mmr32() argument
392 writeq(val, uv_global_mmr32_address(pnode, offset)); in uv_write_global_mmr32()
395 static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset) in uv_read_global_mmr32() argument
397 return readq(uv_global_mmr32_address(pnode, offset)); in uv_read_global_mmr32()
404 static inline volatile void __iomem *uv_global_mmr64_address(int pnode, unsigned long offset) in uv_global_mmr64_address() argument
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| /arch/mips/kernel/ |
| D | gpio_txx9.c | 22 static int txx9_gpio_get(struct gpio_chip *chip, unsigned int offset) in txx9_gpio_get() argument
24 return __raw_readl(&txx9_pioptr->din) & (1 << offset); in txx9_gpio_get()
27 static void txx9_gpio_set_raw(unsigned int offset, int value) in txx9_gpio_set_raw() argument
32 val |= 1 << offset; in txx9_gpio_set_raw()
34 val &= ~(1 << offset); in txx9_gpio_set_raw()
38 static void txx9_gpio_set(struct gpio_chip *chip, unsigned int offset, in txx9_gpio_set() argument
43 txx9_gpio_set_raw(offset, value); in txx9_gpio_set()
48 static int txx9_gpio_dir_in(struct gpio_chip *chip, unsigned int offset) in txx9_gpio_dir_in() argument
52 __raw_writel(__raw_readl(&txx9_pioptr->dir) & ~(1 << offset), in txx9_gpio_dir_in()
59 static int txx9_gpio_dir_out(struct gpio_chip *chip, unsigned int offset, in txx9_gpio_dir_out() argument
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| /arch/x86/include/asm/numachip/ |
| D | numachip_csr.h | 45 static inline void *gcsr_address(int node, unsigned long offset) in gcsr_address() argument
48 CSR_NODE_BITS(node & CSR_NODE_MASK) | (offset & CSR_OFFSET_MASK)); in gcsr_address()
51 static inline void *lcsr_address(unsigned long offset) in lcsr_address() argument
54 CSR_NODE_BITS(0xfff0) | (offset & CSR_OFFSET_MASK)); in lcsr_address()
57 static inline unsigned int read_gcsr(int node, unsigned long offset) in read_gcsr() argument
59 return swab32(readl(gcsr_address(node, offset))); in read_gcsr()
62 static inline void write_gcsr(int node, unsigned long offset, unsigned int val) in write_gcsr() argument
64 writel(swab32(val), gcsr_address(node, offset)); in write_gcsr()
67 static inline unsigned int read_lcsr(unsigned long offset) in read_lcsr() argument
69 return swab32(readl(lcsr_address(offset))); in read_lcsr()
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| /arch/mips/pci/ |
| D | ops-titan-ht.c | 35 int offset, u32 *val) in titan_ht_config_read_dword() argument
42 address = (busno << 16) | (devfn << 8) | (offset & 0xfc) | 0x80000000; in titan_ht_config_read_dword()
67 int offset, int size, u32 *val) in titan_ht_config_read() argument
71 titan_ht_config_read_dword(bus, devfn, offset, &dword); in titan_ht_config_read()
73 dword >>= ((offset & 3) << 3); in titan_ht_config_read()
80 unsigned int devfn, int offset, u32 val) in titan_ht_config_write_dword() argument
87 address = (busno << 16) | (devfn << 8) | (offset & 0xfc) | 0x80000000; in titan_ht_config_write_dword()
106 int offset, int size, u32 val) in titan_ht_config_write() argument
110 titan_ht_config_read_dword(bus, devfn, offset, &val2); in titan_ht_config_write()
112 val1 = val << ((offset & 3) << 3); in titan_ht_config_write()
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| /arch/mips/boot/compressed/ |
| D | uart-16550.c | 13 #define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset)) argument
18 #define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset)) argument
25 static inline unsigned int serial_in(int offset) in serial_in() argument
27 return *((char *)PORT(offset)); in serial_in()
30 static inline void serial_out(int offset, int value) in serial_out() argument
32 *((char *)PORT(offset)) = value; in serial_out()
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| /arch/x86/pci/ |
| D | early.c | 10 u32 read_pci_config(u8 bus, u8 slot, u8 func, u8 offset) in read_pci_config() argument
13 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in read_pci_config()
18 u8 read_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset) in read_pci_config_byte() argument
21 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in read_pci_config_byte()
22 v = inb(0xcfc + (offset&3)); in read_pci_config_byte()
26 u16 read_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset) in read_pci_config_16() argument
29 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in read_pci_config_16()
30 v = inw(0xcfc + (offset&2)); in read_pci_config_16()
34 void write_pci_config(u8 bus, u8 slot, u8 func, u8 offset, in write_pci_config() argument
37 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in write_pci_config()
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| /arch/mips/rb532/ |
| D | gpio.c | 61 unsigned offset, void __iomem *ioaddr) in rb532_set_bit() argument
69 val &= ~(!bitval << offset); /* unset bit if bitval == 0 */ in rb532_set_bit()
70 val |= (!!bitval << offset); /* set bit if bitval == 1 */ in rb532_set_bit()
80 static inline int rb532_get_bit(unsigned offset, void __iomem *ioaddr) in rb532_get_bit() argument
82 return (readl(ioaddr) & (1 << offset)); in rb532_get_bit()
87 static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset) in rb532_gpio_get() argument
92 return rb532_get_bit(offset, gpch->regbase + GPIOD); in rb532_gpio_get()
99 unsigned offset, int value) in rb532_gpio_set() argument
104 rb532_set_bit(value, offset, gpch->regbase + GPIOD); in rb532_gpio_set()
110 static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset) in rb532_gpio_direction_input() argument
[all …]
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| /arch/mips/pmc-sierra/yosemite/ |
| D | ht.c | 55 int offset, u32* val) in titan_ht_config_read_dword() argument
67 address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) | in titan_ht_config_read_dword()
70 address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000; in titan_ht_config_read_dword()
83 int offset, u16* val) in titan_ht_config_read_word() argument
95 address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) | in titan_ht_config_read_word()
98 address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000; in titan_ht_config_read_word()
103 if ((offset & 0x3) == 0) in titan_ht_config_read_word()
104 offset = 0x2; in titan_ht_config_read_word()
106 offset = 0x0; in titan_ht_config_read_word()
109 RM9K_READ_16(data_reg + offset, val); in titan_ht_config_read_word()
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| /arch/x86/platform/ce4100/ |
| D | ce4100.c | 32 static unsigned int mem_serial_in(struct uart_port *p, int offset) in mem_serial_in() argument
34 offset = offset << p->regshift; in mem_serial_in()
35 return readl(p->membase + offset); in mem_serial_in()
48 static unsigned int ce4100_mem_serial_in(struct uart_port *p, int offset) in ce4100_mem_serial_in() argument
52 if (offset == UART_IIR) { in ce4100_mem_serial_in()
53 offset = offset << p->regshift; in ce4100_mem_serial_in()
54 ret = readl(p->membase + offset); in ce4100_mem_serial_in()
68 ret = mem_serial_in(p, offset); in ce4100_mem_serial_in()
72 static void ce4100_mem_serial_out(struct uart_port *p, int offset, int value) in ce4100_mem_serial_out() argument
74 offset = offset << p->regshift; in ce4100_mem_serial_out()
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