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Searched refs:out_le32 (Results 1 – 25 of 43) sorted by relevance

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/arch/powerpc/boot/
Dmv64x60.c183 out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].addr), in mv64x60_cfg_read()
191 out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].addr), in mv64x60_cfg_write()
193 out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].data), val); in mv64x60_cfg_write()
286 out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), 0x3f); in mv64x60_config_ctlr_windows()
287 out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_BAR_ENABLE), 0xf); in mv64x60_config_ctlr_windows()
288 out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), 0xff); in mv64x60_config_ctlr_windows()
306 out_le32((u32 *)(bridge_base + mv64x60_enet2mem[i].lo), base); in mv64x60_config_ctlr_windows()
307 out_le32((u32 *)(bridge_base + mv64x60_enet2mem[i].size), size); in mv64x60_config_ctlr_windows()
308 out_le32((u32 *)(bridge_base + mv64x60_mpsc2mem[i].lo), base); in mv64x60_config_ctlr_windows()
309 out_le32((u32 *)(bridge_base + mv64x60_mpsc2mem[i].size), size); in mv64x60_config_ctlr_windows()
[all …]
Dmpsc.c57 out_le32((u32 *)(mpsc_base + MPSC_CHR_4), MPSC_CHR_4_Z); in mpsc_open()
58 out_le32((u32 *)(mpsc_base + MPSC_CHR_5), in mpsc_open()
60 out_le32((u32 *)(mpsc_base + MPSC_CHR_2), chr2 | MPSC_CHR_2_EH); in mpsc_open()
68 out_le32((u32 *)(mpsc_base + MPSC_CHR_1), chr1 | c); in mpsc_putc()
69 out_le32((u32 *)(mpsc_base + MPSC_CHR_2), chr2 | MPSC_CHR_2_TCS); in mpsc_putc()
82 out_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE), in mpsc_getc()
96 out_le32((u32 *)(mpsc_base + MPSC_CHR_2),MPSC_CHR_2_TA | MPSC_CHR_2_RA); in mpsc_stop_dma()
97 out_le32((u32 *)(sdma_base + SDMA_SDCM), SDMA_SDCM_AR | SDMA_SDCM_AT); in mpsc_stop_dma()
152 out_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE), 0); in mpsc_console_init()
153 out_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE), 0); in mpsc_console_init()
[all …]
Dcuboot-pq2.c194 out_le32(&pci_regs[0][0], mem->pci_addr[1] >> 12); in fixup_pci()
195 out_le32(&pci_regs[0][2], mem->phys_addr >> 12); in fixup_pci()
196 out_le32(&pci_regs[0][4], (~(mem->size[1] - 1) >> 12) | 0xa0000000); in fixup_pci()
198 out_le32(&pci_regs[0][6], mmio->pci_addr[1] >> 12); in fixup_pci()
199 out_le32(&pci_regs[0][8], mmio->phys_addr >> 12); in fixup_pci()
200 out_le32(&pci_regs[0][10], (~(mmio->size[1] - 1) >> 12) | 0x80000000); in fixup_pci()
202 out_le32(&pci_regs[0][12], io->pci_addr[1] >> 12); in fixup_pci()
203 out_le32(&pci_regs[0][14], io->phys_addr >> 12); in fixup_pci()
204 out_le32(&pci_regs[0][16], (~(io->size[1] - 1) >> 12) | 0xc0000000); in fixup_pci()
207 out_le32(&pci_regs[0][58], 0); in fixup_pci()
[all …]
Dcuboot-c2k.c60 out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables); in c2k_bridge_setup()
117 out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), in c2k_bridge_setup()
145 out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0), temp); in c2k_reset()
149 out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp); in c2k_reset()
153 out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp); in c2k_reset()
157 out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2), temp); in c2k_reset()
161 out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp); in c2k_reset()
165 out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp); in c2k_reset()
167 out_le32((u32 *)(bridge_base + MV64x60_GPP_VALUE_SET), in c2k_reset()
Dmv64x60_i2c.c77 out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff); in mv64x60_i2c_control()
83 out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff); in mv64x60_i2c_read_byte()
91 out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_DATA), data & 0xff); in mv64x60_i2c_write_byte()
92 out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff); in mv64x60_i2c_write_byte()
108 out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_SOFT_RESET), 0); in mv64x60_i2c_read()
109 out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_SLAVE_ADDR), 0); in mv64x60_i2c_read()
110 out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_EXT_SLAVE_ADDR), 0); in mv64x60_i2c_read()
111 out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_BAUD), (4 << 3) | 0x4); in mv64x60_i2c_read()
Dprpmc2800.c364 out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables); in prpmc2800_bridge_setup()
395 out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables); in prpmc2800_bridge_setup()
481 out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0), temp); in prpmc2800_reset()
485 out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp); in prpmc2800_reset()
489 out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp); in prpmc2800_reset()
493 out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2), temp); in prpmc2800_reset()
497 out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp); in prpmc2800_reset()
501 out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp); in prpmc2800_reset()
503 out_le32((u32 *)(bridge_base + MV64x60_GPP_VALUE_SET), in prpmc2800_reset()
Dio.h75 static inline void out_le32(volatile unsigned *addr, int val) in out_le32() function
/arch/powerpc/sysdev/
Dmv64x60_pic.c86 out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO, in mv64x60_mask_low()
99 out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO, in mv64x60_unmask_low()
123 out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI, in mv64x60_mask_high()
136 out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI, in mv64x60_unmask_high()
160 out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK, in mv64x60_mask_gpp()
173 out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK, in mv64x60_mask_ack_gpp()
175 out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE, in mv64x60_mask_ack_gpp()
188 out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK, in mv64x60_unmask_gpp()
257 out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK, in mv64x60_init_irq()
259 out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO, in mv64x60_init_irq()
[all …]
Dmv64x60_udbg.c39 out_le32(mpsc_base + MPSC_0_CR1_OFFSET, c); in mv64x60_udbg_putc()
40 out_le32(mpsc_base + MPSC_0_CR2_OFFSET, MPSC_CHR_2_TCS); in mv64x60_udbg_putc()
58 out_le32(mpsc_intr_cause, cause & ~MPSC_INTR_CAUSE_RCC); in mv64x60_udbg_getc()
Dgrackle.c39 out_le32(bp->cfg_data, val); in grackle_set_stg()
52 out_le32(bp->cfg_data, val); in grackle_set_loop_snoop()
Dppc4xx_pci.c1697 out_le32((u32 *)(addr + offset), val); in ppc4xx_pciex_write_config()
1742 out_le32(mbase + PECFG_POM0LAH, pciah); in ppc4xx_setup_one_pciex_POM()
1743 out_le32(mbase + PECFG_POM0LAL, pcial); in ppc4xx_setup_one_pciex_POM()
1762 out_le32(mbase + PECFG_POM1LAH, pciah); in ppc4xx_setup_one_pciex_POM()
1763 out_le32(mbase + PECFG_POM1LAL, pcial); in ppc4xx_setup_one_pciex_POM()
1771 out_le32(mbase + PECFG_POM2LAH, pciah); in ppc4xx_setup_one_pciex_POM()
1772 out_le32(mbase + PECFG_POM2LAL, pcial); in ppc4xx_setup_one_pciex_POM()
1860 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa)); in ppc4xx_configure_pciex_PIMs()
1861 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa) | in ppc4xx_configure_pciex_PIMs()
1865 out_le32(mbase + PECFG_BAR1MPA, 0); in ppc4xx_configure_pciex_PIMs()
[all …]
Dindirect_pci.c59 out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | in indirect_read_config()
117 out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | in indirect_write_config()
145 out_le32(cfg_data, val); in indirect_write_config()
/arch/powerpc/platforms/embedded6xx/
Dc2k.c77 out_le32(mv64x60_mpp_reg_base + MV64x60_MPP_CNTL_0, temp); in c2k_reset_board()
81 out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_LEVEL_CNTL, temp); in c2k_reset_board()
85 out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_IO_CNTL, temp); in c2k_reset_board()
89 out_le32(mv64x60_mpp_reg_base + MV64x60_MPP_CNTL_2, temp); in c2k_reset_board()
93 out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_LEVEL_CNTL, temp); in c2k_reset_board()
97 out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_IO_CNTL, temp); in c2k_reset_board()
99 out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_VALUE_SET, 0x00080004); in c2k_reset_board()
Dprpmc2800.c77 out_le32(mv64x60_mpp_reg_base + MV64x60_MPP_CNTL_0, temp); in prpmc2800_reset_board()
81 out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_LEVEL_CNTL, temp); in prpmc2800_reset_board()
85 out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_IO_CNTL, temp); in prpmc2800_reset_board()
89 out_le32(mv64x60_mpp_reg_base + MV64x60_MPP_CNTL_2, temp); in prpmc2800_reset_board()
93 out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_LEVEL_CNTL, temp); in prpmc2800_reset_board()
97 out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_IO_CNTL, temp); in prpmc2800_reset_board()
99 out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_VALUE_SET, 0x00080004); in prpmc2800_reset_board()
/arch/powerpc/platforms/pasemi/
Diommu.c106 out_le32(iob+IOB_AT_INVAL_TLB_REG, bus_addr >> 14); in iobmap_build()
130 out_le32(iob+IOB_AT_INVAL_TLB_REG, bus_addr >> 14); in iobmap_free()
212 out_le32(iob+IOB_XLT_L1_REGBASE+i*4, regword); in iob_init()
219 out_le32(iob+IOB_AD_REG, regword); in iob_init()
224 out_le32(iob+IOBCOM_REG, regword); in iob_init()
Dgpio_mdio.c51 out_le32(gpio_regs+0x10, 1 << MDIO_PIN(bus)); in mdio_lo()
56 out_le32(gpio_regs, 1 << MDIO_PIN(bus)); in mdio_hi()
61 out_le32(gpio_regs+0x10, 1 << MDC_PIN(bus)); in mdc_lo()
66 out_le32(gpio_regs, 1 << MDC_PIN(bus)); in mdc_hi()
71 out_le32(gpio_regs+0x20, (1 << MDC_PIN(bus)) | (1 << MDIO_PIN(bus))); in mdio_active()
76 out_le32(gpio_regs+0x30, (1 << MDIO_PIN(bus))); in mdio_tristate()
Dpci.c87 out_le32(dummy, 0); in workaround_5945()
89 out_le32(addr, tmp); in workaround_5945()
173 out_le32(addr, val); in pa_pxp_write_config()
Ddma_lib.c69 out_le32(iob_regs+reg, val); in pasemi_write_iob_reg()
90 out_le32(mac_regs[intf]+reg, val); in pasemi_write_mac_reg()
109 out_le32(dma_regs+reg, val); in pasemi_write_dma_reg()
/arch/powerpc/platforms/powermac/
Dpic.c90 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]); in pmac_mask_and_ack_irq()
91 out_le32(&pmac_irq_hw[i]->ack, bit); in pmac_mask_and_ack_irq()
111 out_le32(&pmac_irq_hw[i]->ack, bit); in pmac_ack_irq()
125 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]); in __pmac_set_irq_mask()
155 out_le32(&pmac_irq_hw[i]->ack, bit); in pmac_startup_irq()
384 out_le32(&pmac_irq_hw[i]->enable, 0); in pmac_pic_probe_oldstyle()
618 out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]); in pmacpic_suspend()
620 out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]); in pmacpic_suspend()
633 out_le32(&pmac_irq_hw[0]->enable, 0); in pmacpic_resume()
635 out_le32(&pmac_irq_hw[1]->enable, 0); in pmacpic_resume()
Dpci.c151 out_le32(hose->cfg_addr, caddr); in macrisc_cfg_access()
216 out_le32(addr, val); in macrisc_write_config()
450 swap ? out_le32(addr, val) : out_be32(addr, val); in u3_ht_write_config()
487 out_le32(hose->cfg_addr, caddr); in u4_pcie_cfg_access()
552 out_le32(addr, val); in u4_pcie_write_config()
591 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID); in init_bandit()
597 out_le32(bp->cfg_addr, in init_bandit()
610 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC); in init_bandit()
617 out_le32(bp->cfg_data, magic); in init_bandit()
/arch/powerpc/include/asm/
Ddbdma.h96 out_le32(&((regs)->control), (RUN|FLUSH)<<16); \
102 out_le32(&((regs)->control), (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);\
/arch/microblaze/pci/
Dindirect_pci.c54 out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | in indirect_read_config()
108 out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | in indirect_write_config()
136 out_le32(cfg_data, val); in indirect_write_config()
/arch/powerpc/platforms/maple/
Dpci.c114 out_le32(hose->cfg_addr, caddr); in u3_agp_cfg_access()
177 out_le32(addr, val); in u3_agp_write_config()
327 out_le32(addr, val); in u3_ht_write_config()
368 out_le32(hose->cfg_addr, caddr); in u4_pcie_cfg_access()
432 out_le32(addr, val); in u4_pcie_write_config()
/arch/xtensa/include/asm/
Dio.h182 # define out_le32(b, addr) *(u32*)(addr) = _swapl(b) macro
189 # define out_le32(b, addr) *(u32*)(addr) = (b) macro
/arch/powerpc/platforms/chrp/
Dpci.c81 out_le32(cfg_data, val); in gg2_write_config()
149 out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN | in hydra_init()

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