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Searched refs:outb_p (Results 1 – 25 of 47) sorted by relevance

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/arch/x86/kernel/
Dmca_32.c181 outb_p(0, MCA_ADAPTER_SETUP_REG); in mca_pc_read_pos()
182 outb_p(mca_dev->pos_register, MCA_MOTHERBOARD_SETUP_REG); in mca_pc_read_pos()
185 outb_p(0xff, MCA_MOTHERBOARD_SETUP_REG); in mca_pc_read_pos()
190 outb_p(0xff, MCA_MOTHERBOARD_SETUP_REG); in mca_pc_read_pos()
194 outb_p(0x8|(mca_dev->slot & 0xf), MCA_ADAPTER_SETUP_REG); in mca_pc_read_pos()
196 outb_p(0, MCA_ADAPTER_SETUP_REG); in mca_pc_read_pos()
217 outb_p(0xff, MCA_MOTHERBOARD_SETUP_REG); in mca_pc_write_pos()
221 outb_p(0x8|(mca_dev->slot&0xf), MCA_ADAPTER_SETUP_REG); in mca_pc_write_pos()
222 outb_p(byte, MCA_POS_REG(reg)); in mca_pc_write_pos()
223 outb_p(0, MCA_ADAPTER_SETUP_REG); in mca_pc_write_pos()
[all …]
Dtime.c64 outb_p(inb_p(0x61)| 0x80, 0x61); in timer_interrupt()
/arch/x86/platform/visws/
Dvisws_quirks.c264 outb_p(SIO_DEV_SEL, SIO_INDEX); in visws_early_detect()
265 outb_p(SIO_GP_DEV, SIO_DATA); /* Talk to GPIO regs. */ in visws_early_detect()
267 outb_p(SIO_DEV_MSB, SIO_INDEX); in visws_early_detect()
268 outb_p(SIO_GP_MSB, SIO_DATA); /* MSB of GPIO base address */ in visws_early_detect()
270 outb_p(SIO_DEV_LSB, SIO_INDEX); in visws_early_detect()
271 outb_p(SIO_GP_LSB, SIO_DATA); /* LSB of GPIO base address */ in visws_early_detect()
273 outb_p(SIO_DEV_ENB, SIO_INDEX); in visws_early_detect()
274 outb_p(1, SIO_DATA); /* Enable GPIO registers. */ in visws_early_detect()
281 outb_p(SIO_DEV_SEL, SIO_INDEX); in visws_early_detect()
282 outb_p(SIO_PM_DEV, SIO_DATA); /* Talk to GPIO regs. */ in visws_early_detect()
[all …]
/arch/alpha/include/asm/
Dmc146818rtc.h19 outb_p((addr),RTC_PORT(0)); \
23 outb_p((addr),RTC_PORT(0)); \
24 outb_p((val),RTC_PORT(1)); \
/arch/sparc/include/asm/
Dmc146818rtc_32.h19 outb_p((addr),RTC_PORT(0)); \
23 outb_p((addr),RTC_PORT(0)); \
24 outb_p((val),RTC_PORT(1)); \
Dmc146818rtc_64.h20 outb_p((addr),RTC_PORT(0)); \
24 outb_p((addr),RTC_PORT(0)); \
25 outb_p((val),RTC_PORT(1)); \
/arch/m32r/include/asm/
Dmc146818rtc.h19 outb_p((addr),RTC_PORT(0)); \
23 outb_p((addr),RTC_PORT(0)); \
24 outb_p((val),RTC_PORT(1)); \
/arch/powerpc/include/asm/
Dmc146818rtc.h27 outb_p((addr),RTC_PORT(0)); \
31 outb_p((addr),RTC_PORT(0)); \
32 outb_p((val),RTC_PORT(1)); \
Dfloppy.h17 #define fd_outb(value,port) outb_p(value,port)
69 outb_p(*lptr, virtual_dma_port+5); in floppy_hardint()
/arch/arm/include/asm/
Dmc146818rtc.h22 outb_p((addr),RTC_PORT(0)); \
26 outb_p((addr),RTC_PORT(0)); \
27 outb_p((val),RTC_PORT(1)); \
/arch/mips/include/asm/mach-loongson/
Dmc146818rtc.h20 outb_p(addr, RTC_PORT(0)); in CMOS_READ()
26 outb_p(addr, RTC_PORT(0)); in CMOS_WRITE()
27 outb_p(data, RTC_PORT(1)); in CMOS_WRITE()
/arch/mips/include/asm/mach-generic/
Dmc146818rtc.h20 outb_p(addr, RTC_PORT(0)); in CMOS_READ()
26 outb_p(addr, RTC_PORT(0)); in CMOS_WRITE()
27 outb_p(data, RTC_PORT(1)); in CMOS_WRITE()
Dfloppy.h37 outb_p(value, port); in fd_outb()
/arch/mips/kernel/
Di8259.c263 outb_p(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */ in init_8259A()
264 …outb_p(I8259A_IRQ_BASE + 0, PIC_MASTER_IMR); /* ICW2: 8259A-1 IR0 mapped to I8259A_IRQ_BASE + 0x00… in init_8259A()
265 outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */ in init_8259A()
267 outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR); in init_8259A()
269 outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR); in init_8259A()
271 outb_p(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */ in init_8259A()
272 …outb_p(I8259A_IRQ_BASE + 8, PIC_SLAVE_IMR); /* ICW2: 8259A-2 IR0 mapped to I8259A_IRQ_BASE + 0x08 … in init_8259A()
273 outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR); /* 8259A-2 is a slave on master's IR2 */ in init_8259A()
274 …outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be inve… in init_8259A()
/arch/x86/include/asm/
Dmach_timer.h35 outb_p(CALIBRATE_LATCH & 0xff, 0x42); /* LSB of count */ in mach_prepare_counter()
36 outb_p(CALIBRATE_LATCH >> 8, 0x42); /* MSB of count */ in mach_prepare_counter()
Dfloppy.h35 #define fd_outb(value, port) outb_p(value, port)
84 outb_p(*lptr, virtual_dma_port + 5); in floppy_hardint()
/arch/sh/boards/mach-se/770x/
Dsetup.c23 outb_p(index, INDEX_PORT); in smsc_config()
24 outb_p(data, DATA_PORT); in smsc_config()
30 outb_p(CONFIG_ENTER, CONFIG_PORT); in smsc_setup()
31 outb_p(CONFIG_ENTER, CONFIG_PORT); in smsc_setup()
63 outb_p(CONFIG_EXIT, CONFIG_PORT); in smsc_setup()
/arch/mips/include/asm/mach-jazz/
Dmc146818rtc.h24 outb_p(addr, RTC_PORT(0)); in CMOS_READ()
30 outb_p(addr, RTC_PORT(0)); in CMOS_WRITE()
/arch/powerpc/platforms/maple/
Dtime.c47 outb_p(addr, maple_rtc_addr); in maple_clock_read()
53 outb_p(addr, maple_rtc_addr); in maple_clock_write()
54 outb_p(val, maple_rtc_addr+1); in maple_clock_write()
Dsetup.c118 outb_p(*maple_nvram_command, maple_nvram_base + *maple_nvram_offset); in maple_restart()
145 outb_p(*maple_nvram_command, maple_nvram_base + *maple_nvram_offset); in maple_power_off()
/arch/mips/sni/
Dreset.c37 outb_p(0xfe, 0x64); /* pulse reset low */ in sni_machine_restart()
Dtime.c101 outb_p(0x34, 0x43); in dosample()
102 outb_p(SNI_8254_TCSAMP_COUNTER & 0xff, 0x40); in dosample()
/arch/powerpc/platforms/
Dfsl_uli1575.c170 outb_p(0x7c, 0x72); in quirk_final_uli1575()
171 outb_p(RTC_ALARM_DONT_CARE, 0x73); in quirk_final_uli1575()
173 outb_p(0x7d, 0x72); in quirk_final_uli1575()
174 outb_p(RTC_ALARM_DONT_CARE, 0x73); in quirk_final_uli1575()
/arch/m68k/include/asm/
Dfloppy.h78 outb_p(value, port); in fd_outb()
218 outb_p(*lptr, virtual_dma_port+5); in floppy_hardint()
Dmcfne.h130 #undef outb_p
140 #define outb_p ne2000_outb macro

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