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Searched refs:outl (Results 1 – 25 of 73) sorted by relevance

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/arch/sh/drivers/pci/
Dpci-dreamcast.c72 outl(0x5a14a501, GAPSPCI_REGS+0x18); in gapspci_init()
80 outl(0x01000000, GAPSPCI_REGS+0x20); in gapspci_init()
81 outl(0x01000000, GAPSPCI_REGS+0x24); in gapspci_init()
83 outl(GAPSPCI_DMA_BASE, GAPSPCI_REGS+0x28); in gapspci_init()
84 outl(GAPSPCI_DMA_BASE+GAPSPCI_DMA_SIZE, GAPSPCI_REGS+0x2c); in gapspci_init()
86 outl(1, GAPSPCI_REGS+0x14); in gapspci_init()
87 outl(1, GAPSPCI_REGS+0x34); in gapspci_init()
91 outl(0x00000000, GAPSPCI_BBA_CONFIG+0x30); in gapspci_init()
95 outl(0x00002001, GAPSPCI_BBA_CONFIG+0x10); in gapspci_init()
96 outl(0x01000000, GAPSPCI_BBA_CONFIG+0x14); in gapspci_init()
/arch/mips/pnx8550/common/
Dpci.c89 outl(pci_mem_resource.start, PCI_BASE | PCI_BASE1_LO); in pnx8550_pci_setup()
90 outl(pci_mem_resource.end + 1, PCI_BASE | PCI_BASE1_HI); in pnx8550_pci_setup()
91 outl(pci_io_resource.start, PCI_BASE | PCI_BASE2_LO); in pnx8550_pci_setup()
92 outl(pci_io_resource.end, PCI_BASE | PCI_BASE2_HI); in pnx8550_pci_setup()
95 outl(0x00000001, PCI_BASE | PCI_IO); in pnx8550_pci_setup()
98 outl(0xca, PCI_BASE | PCI_UNLOCKREG); in pnx8550_pci_setup()
105 outl(0x00000000, PCI_BASE | PCI_BASE10); in pnx8550_pci_setup()
112 outl(0x1be00000, PCI_BASE | PCI_BASE14); /* PNX MMIO */ in pnx8550_pci_setup()
113 outl(PNX8550_NAND_BASE_ADDR, PCI_BASE | PCI_BASE18); /* XIO */ in pnx8550_pci_setup()
115 outl(PCI_EN_TA | in pnx8550_pci_setup()
[all …]
/arch/score/kernel/
Dtime.c36 outl(1, P_TIMER0_CPP_REG); in timer_interrupt()
51 outl((TMR_M_PERIODIC | TMR_IE_ENABLE), P_TIMER0_CTRL); in score_timer_set_next_event()
52 outl(delta, P_TIMER0_PRELOAD); in score_timer_set_next_event()
53 outl(inl(P_TIMER0_CTRL) | TMR_ENABLE, P_TIMER0_CTRL); in score_timer_set_next_event()
63 outl((TMR_M_PERIODIC | TMR_IE_ENABLE), P_TIMER0_CTRL); in score_timer_set_mode()
64 outl(SYSTEM_CLOCK/HZ, P_TIMER0_PRELOAD); in score_timer_set_mode()
65 outl(inl(P_TIMER0_CTRL) | TMR_ENABLE, P_TIMER0_CTRL); in score_timer_set_mode()
/arch/x86/platform/olpc/
Dolpc-xo1-pm.c77 outl(saved_sci_mask, acpi_base + CS5536_PM1_STS); in xo1_power_state_enter()
97 outl(wakeup_mask << 16, acpi_base + CS5536_PM1_STS); in xo1_do_sleep()
114 outl(0x40000000, pms_base + CS5536_PM_SCLK); in xo1_power_off()
115 outl(0x40000000, pms_base + CS5536_PM_IN_SLPCTL); in xo1_power_off()
116 outl(0x40000000, pms_base + CS5536_PM_WKXD); in xo1_power_off()
117 outl(0x40000000, pms_base + CS5536_PM_WKD); in xo1_power_off()
120 outl(0x0002ffff, pms_base + CS5536_PM_SSC); in xo1_power_off()
121 outl(0xffffffff, acpi_base + CS5536_PM_GPE0_STS); in xo1_power_off()
124 outl(0x00002000, acpi_base + CS5536_PM1_CNT); in xo1_power_off()
/arch/x86/pci/
Dearly.c13 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in read_pci_config()
21 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in read_pci_config_byte()
29 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in read_pci_config_16()
37 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in write_pci_config()
38 outl(val, 0xcfc); in write_pci_config()
43 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in write_pci_config_byte()
49 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in write_pci_config_16()
Ddirect.c32 outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8); in pci_conf1_read()
61 outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8); in pci_conf1_write()
71 outl((u32)value, 0xCFC); in pci_conf1_write()
165 outl((u32)value, PCI_CONF2_ADDRESS(dev, reg)); in pci_conf2_write()
233 outl(0x80000000, 0xCF8); in pci_check_type1()
237 outl(tmp, 0xCF8); in pci_check_type1()
/arch/mips/pci/
Dops-sni.c79 outl(val, PCIMT_CONFIG_DATA); in pcimt_write()
96 outl((1 << 31) | ((busno & 0xff) << 16) | ((devfn & 0xff) << 8) | (reg & 0xfc), 0xcf8); in pcit_set_config_address()
112 outl(inl(0xcfc) | 0xc0000000, 0xcfc); in pcit_read()
115 outl(0xffffffff, 0xcfc); in pcit_read()
153 outl(val, PCIMT_CONFIG_DATA); in pcit_write()
Dops-pnx8550.c38 outl(pci_stat, PCI_BASE | PCI_GPPM_ICLR); in clear_status()
66 outl(ioaddr, PCI_BASE | PCI_GPPM_ADDR); in config_access()
69 outl(*val, PCI_BASE | PCI_GPPM_WDAT); in config_access()
71 outl(INIT_PCI_CYCLE | pci_cmd | (pci_mode & PCI_BYTE_ENABLE_MASK), in config_access()
/arch/m32r/kernel/
Dtime.c184 outl((M32R_MFTMOD_CC_MASK | M32R_MFTMOD_TCCR \ in time_init()
186 outl(latch, M32R_MFT2RLD_PORTL); in time_init()
187 outl(latch, M32R_MFT2CUT_PORTL); in time_init()
188 outl(0, M32R_MFT2CMPRLD_PORTL); in time_init()
189 outl((M32R_MFTCR_MFT2MSK|M32R_MFTCR_MFT2EN), M32R_MFTCR_PORTL); in time_init()
/arch/arm/common/
Dvia82c505.c20 outl(CONFIG_CMD(bus,devfn,where),0xCF8); in via82c505_read_config()
39 outl(CONFIG_CMD(bus,devfn,where),0xCF8); in via82c505_write_config()
48 outl(value, 0xCFC); in via82c505_write_config()
/arch/mips/sgi-ip22/
Dip22-eisa.c129 outl(0x0000FFFF, EIU_PREMPT_REG); in ip22_eisa_init()
130 outl(1, EIU_QUIET_REG); in ip22_eisa_init()
131 outl(0x40f3c07F, EIU_MODE_REG); in ip22_eisa_init()
/arch/m32r/platforms/oaks32r/
Dsetup.c27 outl(data, port); in disable_oaks32r_irq()
36 outl(data, port); in enable_oaks32r_irq()
54 outl(M32R_ICUCR_ILEVEL7, port); in shutdown_oaks32r()
/arch/parisc/lib/
Dio.c423 outl(le32_to_cpu(*(unsigned int *)p), port); in outsl()
438 outl (le32_to_cpu(l << 16 | l2 >> 16), port); in outsl()
442 outl (le32_to_cpu(l << 16 | l2), port); in outsl()
456 outl (le32_to_cpu(l | l2 >> 24), port); in outsl()
460 outl (le32_to_cpu(l | l2), port); in outsl()
472 outl (le32_to_cpu(l | l2 >> 8), port); in outsl()
478 outl (le32_to_cpu(l | l2), port); in outsl()
/arch/m32r/platforms/m32104ut/
Dsetup.c29 outl(data, port); in disable_m32104ut_irq()
38 outl(data, port); in enable_m32104ut_irq()
56 outl(M32R_ICUCR_ILEVEL7, port); in shutdown_m32104ut_irq()
/arch/sh/boards/mach-dreamcast/
Dirq.c71 outl(mask, emr); in disable_systemasic_irq()
83 outl(mask, emr); in enable_systemasic_irq()
92 outl((1 << EVENT_BIT(irq)), esr); in mask_ack_systemasic_irq()
/arch/arm/include/asm/hardware/
Diomd.h177 outl (SCREEN_START + start, VDMA_START); \
178 outl (SCREEN_START + end - VDMA_XFERSIZE, VDMA_END); \
181 outl (SCREEN_START + offset, VDMA_INIT); \
/arch/x86/kernel/
Dreboot_fixups_32.c37 outl(0x80003840, 0xCF8); in rdc321x_reset()
42 outl(i, 0xCFC); in rdc321x_reset()
/arch/m32r/platforms/mappi/
Dsetup.c28 outl(data, port); in disable_mappi_irq()
37 outl(data, port); in enable_mappi_irq()
55 outl(M32R_ICUCR_ILEVEL7, port); in shutdown_mappi()
/arch/mips/loongson/lemote-2f/
Dreset.c68 outl(val, gpio_base + GPIOL_OUT_EN); in fl2f_shutdown()
73 outl(val, gpio_base + GPIOL_OUT_VAL); in fl2f_shutdown()
/arch/m32r/platforms/mappi2/
Dsetup.c32 outl(data, port); in disable_mappi2_irq()
45 outl(data, port); in enable_mappi2_irq()
63 outl(M32R_ICUCR_ILEVEL7, port); in shutdown_mappi2()
/arch/alpha/kernel/
Dsys_takara.c43 outl(mask & 0xffff0000UL, regaddr); in takara_update_irq_hw()
129 outl(ctlreg, 0x500); in takara_init_irq()
133 outl(ctlreg, 0x500); in takara_init_irq()
/arch/mn10300/kernel/
Dio.c26 outl(val, addr); in __outsl()
/arch/m32r/platforms/mappi3/
Dsetup.c32 outl(data, port); in disable_mappi3_irq()
45 outl(data, port); in enable_mappi3_irq()
63 outl(M32R_ICUCR_ILEVEL7, port); in shutdown_mappi3()
/arch/parisc/include/asm/
Dio.h238 #define outl_p outl
254 extern void outl(unsigned int b, int addr);
261 #define outl eisa_out32 macro
283 #define outl(x, y) BUG() macro
/arch/x86/platform/scx200/
Dscx200_32.c100 outl(index, scx200_gpio_base + 0x20); in scx200_gpio_configure()
104 outl(new_config, scx200_gpio_base + 0x24); in scx200_gpio_configure()

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