| /arch/m68k/fpsp040/ |
| D | skeleton.S | 89 | bug, if an E1 snan, ovfl, or unfl occurred, and the process was
91 | return was inex, rather than the correct exception. The snan, ovfl,
93 | fix is to check for E1, and the existence of one of snan, ovfl,
117 btstb #ovfl_bit,2(%sp) |test for ovfl
122 bra ovfl
175 .global ovfl symbol
176 ovfl: label
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| D | gen_except.S | 18 | ovfl
25 | reported if ovfl occurs and the ovfl enable bit is not
210 | the case of the ovfl exc without the ovfl enabled, but with
214 btstb #inex2_bit,FPCR_ENABLE(%a6) |check for ovfl/inex2 case
216 btstb #ovfl_bit,FPSR_EXCEPT(%a6) |now check ovfl
360 bfextu USER_FPSR(%a6){#17:#4},%d0 |get snan/operr/ovfl/unfl bits
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| D | scale.S | 103 bges ovfl
112 ovfl: label
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| D | res_func.S | 962 | The result has overflowed to $7fff exponent. Set I, ovfl,
1143 | The result has overflowed to $7fff exponent. Set I, ovfl,
1459 | that gen_except will have a correctly signed value for ovfl/unfl
1477 | that gen_except will have a correctly signed value for ovfl/unfl
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| D | bugfix.S | 170 | nu-generated ovfl, unfl, or inex exception. If the version
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| /arch/m68k/ifpsp060/ |
| D | TEST.DOC | 145 0x10: FP enabled snan/operr/ovfl/unfl/dz/inex
159 FP enabled: tests enabled snan/operr/ovfl/unfl/dz/inex.
162 exercises _fpsp_{snan,operr,ovfl,unfl,dz,inex}() and
163 _real_{snan,operr,ovfl,unfl,dz,inex}(). the test expects
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| /arch/parisc/math-emu/ |
| D | fcnvff.c | 259 Sgl_setwrapped_exponent(result,dest_exponent,ovfl); in dbl_to_sgl_fcnvff()
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| D | sfmpy.c | 278 Sgl_setwrapped_exponent(result,dest_exponent,ovfl); in sgl_fmpy()
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| D | sfdiv.c | 291 Sgl_setwrapped_exponent(result,dest_exponent,ovfl); in sgl_fdiv()
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| D | sfsub.c | 500 Sgl_setwrapped_exponent(result,result_exponent,ovfl); in sgl_fsub()
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| D | sfadd.c | 497 Sgl_setwrapped_exponent(result,result_exponent,ovfl); in sgl_fadd()
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| D | dfmpy.c | 292 Dbl_setwrapped_exponent(resultp1,dest_exponent,ovfl); in dbl_fmpy()
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| D | dfdiv.c | 297 Dbl_setwrapped_exponent(resultp1,dest_exponent,ovfl); in dbl_fdiv()
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| D | dfsub.c | 505 Dbl_setwrapped_exponent(resultp1,result_exponent,ovfl); in dbl_fsub()
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| D | dfadd.c | 502 Dbl_setwrapped_exponent(resultp1,result_exponent,ovfl); in dbl_fadd()
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| D | fmpyfadd.c | 677 Dbl_setwrapped_exponent(resultp1,result_exponent,ovfl); in dbl_fmpyfadd()
1337 Dbl_setwrapped_exponent(resultp1,result_exponent,ovfl);
1978 Sgl_setwrapped_exponent(resultp1,result_exponent,ovfl);
2620 Sgl_setwrapped_exponent(resultp1,result_exponent,ovfl);
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| D | sgl_float.h | 193 #define ovfl - macro
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| D | dbl_float.h | 316 #define ovfl - macro
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| /arch/m68k/ifpsp060/src/ |
| D | fpsp.S | 1674 # for snan,operr,ovfl,unfl, src op is still in FP_SRC so just
11677 or.l &ovfl_inx_mask,USER_FPSR(%a6) # set ovfl/aovfl/ainex
13649 or.l &ovfl_inx_mask,USER_FPSR(%a6) # set ovfl/aovfl/ainex
13985 cmpi.l %d0,&0x3fff-0x7ffe # would result ovfl?
14036 or.l &ovfl_inx_mask, USER_FPSR(%a6) # set ovfl/aovfl/ainex
14389 or.w &ovfl_inx_mask,2+USER_FPSR(%a6) # set ovfl/aovfl/ainex
14712 long 0x7fff # ext ovfl
14713 long 0x407f # sgl ovfl
14714 long 0x43ff # dbl ovfl
14722 or.l &ovfl_inx_mask,USER_FPSR(%a6) # set ovfl/aovfl/ainex
[all …]
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| D | ftest.S | 117 ### ovfl non-maskable
191 ### ovfl
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| D | pfpsp.S | 1673 # for snan,operr,ovfl,unfl, src op is still in FP_SRC so just
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| D | fplsp.S | 519 set OVFL_VEC, 0xd4 # ovfl vector offset
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