Searched refs:pChipcHw (Results 1 – 5 of 5) sorted by relevance
73 …if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDI… in chipcHw_getClockFrequency()78 ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> in chipcHw_getClockFrequency()89 ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> in chipcHw_getClockFrequency()95 ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> in chipcHw_getClockFrequency()100 pPLLReg = &pChipcHw->DDRClock; in chipcHw_getClockFrequency()104 pPLLReg = &pChipcHw->ARMClock; in chipcHw_getClockFrequency()108 pPLLReg = &pChipcHw->ESWClock; in chipcHw_getClockFrequency()112 pPLLReg = &pChipcHw->VPMClock; in chipcHw_getClockFrequency()116 pPLLReg = &pChipcHw->ESW125Clock; in chipcHw_getClockFrequency()120 pPLLReg = &pChipcHw->UARTClock; in chipcHw_getClockFrequency()[all …]
76 pChipcHw->PLLConfig2 = in chipcHw_pll2Enable()90 pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE; in chipcHw_pll2Enable()93 pChipcHw->PLLPreDivider2 = pllPreDivider2; in chipcHw_pll2Enable()95 pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f; in chipcHw_pll2Enable()98 pChipcHw->PLLControl12 = 0x38000700; in chipcHw_pll2Enable()99 pChipcHw->PLLControl22 = 0x00000015; in chipcHw_pll2Enable()103 pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET | in chipcHw_pll2Enable()108 pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET | in chipcHw_pll2Enable()122 pChipcHw->PLLConfig2 &= in chipcHw_pll2Enable()131 while (!(pChipcHw->PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED)) in chipcHw_pll2Enable()[all …]
53 pChipcHw->UARTClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT; in chipcHw_reset()54 pChipcHw->SPIClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT; in chipcHw_reset()
50 return pChipcHw->ChipId; in chipcHw_getChipId()62 if ((pChipcHw-> in chipcHw_enableSpreadSpectrum()96 return (pChipcHw-> in chipcHw_getChipProductId()112 return pChipcHw->ChipId & chipcHw_REG_CHIPID_REV_MASK; in chipcHw_getChipRevisionNumber()128 reg32_modify_or(&pChipcHw->BusIntfClock, mask); in chipcHw_busInterfaceClockEnable()144 reg32_modify_and(&pChipcHw->BusIntfClock, ~mask); in chipcHw_busInterfaceClockDisable()159 return pChipcHw->BusIntfClock; in chipcHw_getBusInterfaceClockStatus()175 reg32_modify_or(&pChipcHw->AudioEnable, mask); in chipcHw_audioChannelEnable()191 reg32_modify_and(&pChipcHw->AudioEnable, ~mask); in chipcHw_audioChannelDisable()218 pChipcHw->SoftReset1 ^= ctrl1; in chipcHw_softResetDisable()[all …]
134 #define pChipcHw ((volatile chipcHw_REG_t *) chipcHw_BASE_ADDRESS) macro257 #define chipcHw_REG_SW_STRAPS ((pChipcHw->PinStraps & 0x0000FC00) >> 10)280 #define chipcHw_REG_GPIO_MUX(pin) (&pChipcHw->GpioMux_0_7 + ((pin) >> 3))287 …RATE(pin) (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pC…299 …NT(pin) (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pC…307 …pin) (((pin) > 42) ? (&pChipcHw->GpioPull_0_15 + (((pin) + 2) >> 4)) : (&p…314 …PE(pin) (((pin) > 42) ? (&pChipcHw->GpioInput_0_31 + (((pin) + 2) >> 5)) : (&…