| /arch/arm/mach-davinci/ |
| D | clock.c | 246 struct pll_data *pll; in clk_sysclk_recalc() local
262 pll = clk->parent->pll_data; in clk_sysclk_recalc()
266 rate = pll->input_rate; in clk_sysclk_recalc()
271 v = __raw_readl(pll->base + clk->div_reg); in clk_sysclk_recalc()
273 plldiv = (v & pll->div_ratio_mask) + 1; in clk_sysclk_recalc()
284 struct pll_data *pll; in davinci_set_sysclk_rate() local
304 pll = clk->parent->pll_data; in davinci_set_sysclk_rate()
310 input = pll->input_rate; in davinci_set_sysclk_rate()
330 if (ratio > pll->div_ratio_mask) in davinci_set_sysclk_rate()
334 v = __raw_readl(pll->base + PLLSTAT); in davinci_set_sysclk_rate()
[all …]
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| D | tnetv107x.c | 116 #define define_pll_clk(cname, pll, divmask, base) \ argument
118 .num = pll, \
135 #define define_pll_div_clk(pll, cname, div) \ argument
136 static struct clk pll##_##cname##_clk = { \
137 .name = #pll "_" #cname "_clk", \
138 .parent = &pll_##pll##_clk, \
649 int pll; in clk_sspll_recalc() local
665 for (pll = 0; pll < N_PLLS; pll++) in clk_sspll_recalc()
666 sspll_regs[pll] = tmp + sspll_regs_base[pll]; in clk_sspll_recalc()
671 pll = clk->pll_data->num; in clk_sspll_recalc()
[all …]
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| /arch/mips/lantiq/xway/ |
| D | clk-xway.c | 70 static inline unsigned int get_input_clock(int pll) in get_input_clock() argument
72 switch (pll) { in get_input_clock()
103 static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den) in cal_dsm() argument
105 u64 res, clock = get_input_clock(pll); in cal_dsm()
112 static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N, in mash_dsm() argument
118 return cal_dsm(pll, num, den); in mash_dsm()
121 static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N, in ssff_dsm_1() argument
127 return cal_dsm(pll, num, den); in ssff_dsm_1()
130 static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N, in ssff_dsm_2() argument
137 return cal_dsm(pll, num, den); in ssff_dsm_2()
[all …]
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| /arch/mips/ath79/ |
| D | clock.c | 38 u32 pll; in ar71xx_clocks_init() local
44 pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG); in ar71xx_clocks_init()
46 div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1; in ar71xx_clocks_init()
49 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; in ar71xx_clocks_init()
52 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; in ar71xx_clocks_init()
55 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; in ar71xx_clocks_init()
64 u32 pll; in ar724x_clocks_init() local
69 pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG); in ar724x_clocks_init()
71 div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); in ar724x_clocks_init()
74 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); in ar724x_clocks_init()
[all …]
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| /arch/arm/mach-msm/ |
| D | acpuclock-arm11.c | 85 int pll; member
298 unsigned int plls_enabled = 0, pll; in acpuclk_set_rate() local
319 while (tgt_s->pll != ACPU_PLL_TCXO && tgt_s->pll != cur_s->pll) in acpuclk_set_rate()
323 if (strt_s->pll != ACPU_PLL_TCXO) in acpuclk_set_rate()
324 plls_enabled |= 1 << strt_s->pll; in acpuclk_set_rate()
328 if (strt_s->pll != tgt_s->pll && tgt_s->pll != ACPU_PLL_TCXO) { in acpuclk_set_rate()
329 rc = pc_pll_request(tgt_s->pll, 1); in acpuclk_set_rate()
332 tgt_s->pll, rc); in acpuclk_set_rate()
335 plls_enabled |= 1 << tgt_s->pll; in acpuclk_set_rate()
379 __FUNCTION__, cur_s->a11clk_khz, cur_s->pll); in acpuclk_set_rate()
[all …]
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| /arch/m68k/q40/ |
| D | config.c | 47 static int q40_get_rtc_pll(struct rtc_pll_info *pll);
48 static int q40_set_rtc_pll(struct rtc_pll_info *pll);
302 static int q40_get_rtc_pll(struct rtc_pll_info *pll) in q40_get_rtc_pll() argument
306 pll->pll_value = tmp & Q40_RTC_PLL_MASK; in q40_get_rtc_pll()
308 pll->pll_value = -pll->pll_value; in q40_get_rtc_pll()
309 pll->pll_max = 31; in q40_get_rtc_pll()
310 pll->pll_min = -31; in q40_get_rtc_pll()
311 pll->pll_posmult = 512; in q40_get_rtc_pll()
312 pll->pll_negmult = 256; in q40_get_rtc_pll()
313 pll->pll_clock = 125829120; in q40_get_rtc_pll()
[all …]
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| /arch/m68k/include/asm/ |
| D | rtc.h | 63 static inline int get_rtc_pll(struct rtc_pll_info *pll) in get_rtc_pll() argument
66 return mach_get_rtc_pll(pll); in get_rtc_pll()
70 static inline int set_rtc_pll(struct rtc_pll_info *pll) in set_rtc_pll() argument
73 return mach_set_rtc_pll(pll); in set_rtc_pll()
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| /arch/c6x/platforms/ |
| D | plldata.c | 172 struct pll_data *pll = &c6x_soc_pll1; in c6455_setup_clocks() local
173 struct clk *sysclks = pll->sysclks; in c6455_setup_clocks()
175 pll->flags = PLL_HAS_PRE | PLL_HAS_MUL; in c6455_setup_clocks()
210 struct pll_data *pll = &c6x_soc_pll1; in c6457_setup_clocks() local
211 struct clk *sysclks = pll->sysclks; in c6457_setup_clocks()
213 pll->flags = PLL_HAS_MUL | PLL_HAS_POST; in c6457_setup_clocks()
260 struct pll_data *pll = &c6x_soc_pll1; in c6472_setup_clocks() local
261 struct clk *sysclks = pll->sysclks; in c6472_setup_clocks()
264 pll->flags = PLL_HAS_MUL; in c6472_setup_clocks()
309 struct pll_data *pll = &c6x_soc_pll1; in c6474_setup_clocks() local
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| D | pll.c | 204 static u32 pll_read(struct pll_data *pll, int reg) in pll_read() argument
206 return soc_readl(pll->base + reg); in pll_read()
212 struct pll_data *pll; in clk_sysclk_recalc() local
224 pll = clk->parent->pll_data; in clk_sysclk_recalc()
228 rate = pll->input_rate; in clk_sysclk_recalc()
243 v = pll_read(pll, clk->div); in clk_sysclk_recalc()
273 struct pll_data *pll = clk->pll_data; in clk_pllclk_recalc() local
279 ctrl = pll_read(pll, PLLCTL); in clk_pllclk_recalc()
280 rate = pll->input_rate = clk->parent->rate; in clk_pllclk_recalc()
287 if (pll->flags & PLL_HAS_MUL) { in clk_pllclk_recalc()
[all …]
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| D | Makefile | 7 obj-y = platform.o cache.o megamod-pic.o pll.o plldata.o timer64.o
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| /arch/avr32/boards/atstk1000/ |
| D | atstk1003.c | 84 struct clk *pll; in atstk1003_setup_extdac() local
89 pll = clk_get(NULL, "pll0"); in atstk1003_setup_extdac()
90 if (IS_ERR(pll)) in atstk1003_setup_extdac()
93 if (clk_set_parent(gclk, pll)) { in atstk1003_setup_extdac()
102 clk_put(pll); in atstk1003_setup_extdac()
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| D | atstk1004.c | 89 struct clk *pll; in atstk1004_setup_extdac() local
94 pll = clk_get(NULL, "pll0"); in atstk1004_setup_extdac()
95 if (IS_ERR(pll)) in atstk1004_setup_extdac()
98 if (clk_set_parent(gclk, pll)) { in atstk1004_setup_extdac()
107 clk_put(pll); in atstk1004_setup_extdac()
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| D | atstk1002.c | 217 struct clk *pll; in atstk1002_setup_extdac() local
222 pll = clk_get(NULL, "pll0"); in atstk1002_setup_extdac()
223 if (IS_ERR(pll)) in atstk1002_setup_extdac()
226 if (clk_set_parent(gclk, pll)) { in atstk1002_setup_extdac()
235 clk_put(pll); in atstk1002_setup_extdac()
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| /arch/arm/plat-s3c24xx/ |
| D | cpu-freq.c | 74 cfg->pll.index = __raw_readl(S3C2410_MPLLCON); in s3c_cpufreq_getcur()
75 cfg->pll.frequency = fclk; in s3c_cpufreq_getcur()
85 unsigned long pll = cfg->pll.frequency; in s3c_cpufreq_calc() local
87 cfg->freq.fclk = pll; in s3c_cpufreq_calc()
88 cfg->freq.hclk = pll / cfg->divs.h_divisor; in s3c_cpufreq_calc()
89 cfg->freq.pclk = pll / cfg->divs.p_divisor; in s3c_cpufreq_calc()
107 pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk, in s3c_cpufreq_show()
161 struct cpufreq_frequency_table *pll) in s3c_cpufreq_settarget() argument
173 cpu_new.pll = pll ? *pll : cpu_cur.pll; in s3c_cpufreq_settarget()
175 if (pll) in s3c_cpufreq_settarget()
[all …]
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| /arch/c6x/boot/dts/ |
| D | tms320c6457.dtsi | 61 compatible = "ti,c6457-pll", "ti,c64x+pll";
63 ti,c64x+pll-bypass-delay = <300>;
64 ti,c64x+pll-reset-delay = <24000>;
65 ti,c64x+pll-lock-delay = <50000>;
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| D | tms320c6474.dtsi | 82 compatible = "ti,c6474-pll", "ti,c64x+pll";
84 ti,c64x+pll-bypass-delay = <120>;
85 ti,c64x+pll-reset-delay = <30000>;
86 ti,c64x+pll-lock-delay = <60000>;
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| D | tms320c6455.dtsi | 71 compatible = "ti,c6455-pll", "ti,c64x+pll";
73 ti,c64x+pll-bypass-delay = <1440>;
74 ti,c64x+pll-reset-delay = <15360>;
75 ti,c64x+pll-lock-delay = <24000>;
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| D | tms320c6472.dtsi | 105 compatible = "ti,c6472-pll", "ti,c64x+pll";
107 ti,c64x+pll-bypass-delay = <200>;
108 ti,c64x+pll-reset-delay = <12000>;
109 ti,c64x+pll-lock-delay = <80000>;
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| /arch/arm/mach-s3c2440/ |
| D | Makefile | 16 obj-$(CONFIG_S3C2440_PLL_12000000) += s3c2440-pll-12000000.o
17 obj-$(CONFIG_S3C2440_PLL_16934400) += s3c2440-pll-16934400.o
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| /arch/powerpc/include/asm/ |
| D | rtc.h | 68 static inline int get_rtc_pll(struct rtc_pll_info *pll) in get_rtc_pll() argument
72 static inline int set_rtc_pll(struct rtc_pll_info *pll) in set_rtc_pll() argument
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| /arch/cris/arch-v32/mach-fs/ |
| D | cpufreq.c | 27 return clk_ctrl.pll ? 200000 : 6000; in cris_freq_get_cpu_frequency()
50 clk_ctrl.pll = 1; in cris_freq_set_cpu_state()
52 clk_ctrl.pll = 0; in cris_freq_set_cpu_state()
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| /arch/cris/arch-v32/mach-a3/ |
| D | cpufreq.c | 27 return clk_ctrl.pll ? 200000 : 6000; in cris_freq_get_cpu_frequency()
53 clk_ctrl.pll = 1; in cris_freq_set_cpu_state()
55 clk_ctrl.pll = 0; in cris_freq_set_cpu_state()
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| /arch/mips/ar7/ |
| D | clock.c | 62 u32 pll; member
178 u32 pll = readl(&clock->pll); in tnetd7300_get_clock() local
182 int mul = ((pll & MUL_MASK) >> MUL_SHIFT) + 1; in tnetd7300_get_clock()
202 if ((pll & PLL_MODE_MASK) == 0) in tnetd7300_get_clock()
205 if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) { in tnetd7300_get_clock()
243 writel(4, &clock->pll); in tnetd7300_set_clock()
244 while (readl(&clock->pll) & PLL_STATUS) in tnetd7300_set_clock()
246 writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll); in tnetd7300_set_clock()
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| /arch/arm/mach-s3c2410/ |
| D | Makefile | 13 obj-$(CONFIG_S3C2410_PLLTABLE) += pll.o
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| /arch/parisc/include/asm/ |
| D | rtc.h | 121 static inline int get_rtc_pll(struct rtc_pll_info *pll) in get_rtc_pll() argument
125 static inline int set_rtc_pll(struct rtc_pll_info *pll) in set_rtc_pll() argument
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