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Searched refs:prio (Results 1 – 25 of 35) sorted by relevance

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/arch/powerpc/sysdev/
Dipic.c40 .prio = IPIC_SIPRR_C,
47 .prio = IPIC_SIPRR_C,
54 .prio = IPIC_SIPRR_C,
61 .prio = IPIC_SIPRR_C,
68 .prio = IPIC_SIPRR_C,
75 .prio = IPIC_SIPRR_C,
82 .prio = IPIC_SIPRR_C,
89 .prio = IPIC_SIPRR_C,
96 .prio = IPIC_SIPRR_D,
103 .prio = IPIC_SIPRR_D,
[all …]
Dehv_pic.c75 unsigned int config, prio, cpu_dest; in ehv_pic_set_affinity() local
80 ev_int_get_config(src, &config, &prio, &cpu_dest); in ehv_pic_set_affinity()
81 ev_int_set_config(src, config, prio, cpuid); in ehv_pic_set_affinity()
116 unsigned int vecpri, vold, vnew, prio, cpu_dest; in ehv_pic_set_irq_type() local
130 ev_int_get_config(src, &vold, &prio, &cpu_dest); in ehv_pic_set_irq_type()
141 prio = 8; in ehv_pic_set_irq_type()
143 ev_int_set_config(src, vecpri, prio, cpu_dest); in ehv_pic_set_irq_type()
Dipic.h53 u8 prio; /* priority register offset from base */ member
/arch/c6x/kernel/
Dirq.c38 unsigned int prio = data->irq; in mask_core_irq() local
40 BUG_ON(prio < 4 || prio >= NR_PRIORITY_IRQS); in mask_core_irq()
43 and_creg(IER, ~(1 << prio)); in mask_core_irq()
49 unsigned int prio = data->irq; in unmask_core_irq() local
52 or_creg(IER, 1 << prio); in unmask_core_irq()
62 asmlinkage void c6x_do_IRQ(unsigned int prio, struct pt_regs *regs) in c6x_do_IRQ() argument
68 BUG_ON(prio < 4 || prio >= NR_PRIORITY_IRQS); in c6x_do_IRQ()
70 generic_handle_irq(prio); in c6x_do_IRQ()
/arch/powerpc/kvm/
Dbook3s.c82 unsigned int prio; in kvmppc_book3s_vec2irqprio() local
85 case 0x100: prio = BOOK3S_IRQPRIO_SYSTEM_RESET; break; in kvmppc_book3s_vec2irqprio()
86 case 0x200: prio = BOOK3S_IRQPRIO_MACHINE_CHECK; break; in kvmppc_book3s_vec2irqprio()
87 case 0x300: prio = BOOK3S_IRQPRIO_DATA_STORAGE; break; in kvmppc_book3s_vec2irqprio()
88 case 0x380: prio = BOOK3S_IRQPRIO_DATA_SEGMENT; break; in kvmppc_book3s_vec2irqprio()
89 case 0x400: prio = BOOK3S_IRQPRIO_INST_STORAGE; break; in kvmppc_book3s_vec2irqprio()
90 case 0x480: prio = BOOK3S_IRQPRIO_INST_SEGMENT; break; in kvmppc_book3s_vec2irqprio()
91 case 0x500: prio = BOOK3S_IRQPRIO_EXTERNAL; break; in kvmppc_book3s_vec2irqprio()
92 case 0x501: prio = BOOK3S_IRQPRIO_EXTERNAL_LEVEL; break; in kvmppc_book3s_vec2irqprio()
93 case 0x600: prio = BOOK3S_IRQPRIO_ALIGNMENT; break; in kvmppc_book3s_vec2irqprio()
[all …]
/arch/unicore32/kernel/
Ddma.c27 puv3_dma_prio prio; member
35 int puv3_request_dma(char *name, puv3_dma_prio prio, in puv3_request_dma() argument
52 if ((dma_channels[i].prio == prio) && in puv3_request_dma()
59 } while (!found && prio--); in puv3_request_dma()
163 dma_channels[i].prio = min((i & 0x7) >> 1, DMA_PRIO_LOW); in puv3_init_dma()
/arch/ia64/kernel/
Dsys_ia64.c83 long prio; in ia64_getpriority() local
85 prio = sys_getpriority(which, who); in ia64_getpriority()
86 if (prio >= 0) { in ia64_getpriority()
88 prio = 20 - prio; in ia64_getpriority()
90 return prio; in ia64_getpriority()
/arch/powerpc/boot/dts/
Dvirtex440-ml507.dts72 xlnx,dcu-rd-ld-cache-plb-prio = <0>;
73 xlnx,dcu-rd-noncache-plb-prio = <0>;
74 xlnx,dcu-rd-touch-plb-prio = <0>;
75 xlnx,dcu-rd-urgent-plb-prio = <0>;
76 xlnx,dcu-wr-flush-plb-prio = <0>;
77 xlnx,dcu-wr-store-plb-prio = <0>;
78 xlnx,dcu-wr-urgent-plb-prio = <0>;
80 xlnx,dma0-plb-prio = <0>;
86 xlnx,dma1-plb-prio = <0>;
92 xlnx,dma2-plb-prio = <0>;
[all …]
Dvirtex440-ml510.dts67 xlnx,dcu-rd-ld-cache-plb-prio = <0x0>;
68 xlnx,dcu-rd-noncache-plb-prio = <0x0>;
69 xlnx,dcu-rd-touch-plb-prio = <0x0>;
70 xlnx,dcu-rd-urgent-plb-prio = <0x0>;
71 xlnx,dcu-wr-flush-plb-prio = <0x0>;
72 xlnx,dcu-wr-store-plb-prio = <0x0>;
73 xlnx,dcu-wr-urgent-plb-prio = <0x0>;
75 xlnx,dma0-plb-prio = <0x0>;
81 xlnx,dma1-plb-prio = <0x0>;
87 xlnx,dma2-plb-prio = <0x0>;
[all …]
/arch/powerpc/platforms/cell/spufs/
Dsched.c86 #define SCALE_PRIO(x, prio) \ argument
87 max(x * (MAX_PRIO - prio) / (MAX_USER_PRIO / 2), MIN_SPU_TIMESLICE)
99 if (ctx->prio < NORMAL_PRIO) in spu_set_timeslice()
100 ctx->time_slice = SCALE_PRIO(DEF_SPU_TIMESLICE * 4, ctx->prio); in spu_set_timeslice()
102 ctx->time_slice = SCALE_PRIO(DEF_SPU_TIMESLICE, ctx->prio); in spu_set_timeslice()
129 if (rt_prio(current->prio)) in __spu_update_sched_info()
130 ctx->prio = current->prio; in __spu_update_sched_info()
132 ctx->prio = current->static_prio; in __spu_update_sched_info()
509 list_add_tail(&ctx->rq, &spu_prio->runq[ctx->prio]); in __spu_add_to_rq()
510 set_bit(ctx->prio, spu_prio->bitmap); in __spu_add_to_rq()
[all …]
/arch/arm/plat-mxc/
Dirq-common.c24 int imx_irq_set_priority(unsigned char irq, unsigned char prio) in imx_irq_set_priority() argument
36 ret = exirq->set_priority(irq, prio); in imx_irq_set_priority()
Dirq-common.h24 int (*set_priority)(unsigned char irq, unsigned char prio);
Davic.c57 static int avic_irq_set_priority(unsigned char irq, unsigned char prio) in avic_irq_set_priority() argument
67 temp |= prio & mask; in avic_irq_set_priority()
/arch/blackfin/kernel/
Dipipe.c169 int prio = __ipipe_get_irq_priority(irq); in __ipipe_enable_irqdesc() local
173 atomic_inc_return(&__ipipe_irq_lvdepth[prio]) == 1) in __ipipe_enable_irqdesc()
174 __set_bit(prio, &__ipipe_irq_lvmask); in __ipipe_enable_irqdesc()
180 int prio = __ipipe_get_irq_priority(irq); in __ipipe_disable_irqdesc() local
183 atomic_dec_and_test(&__ipipe_irq_lvdepth[prio])) in __ipipe_disable_irqdesc()
184 __clear_bit(prio, &__ipipe_irq_lvmask); in __ipipe_disable_irqdesc()
/arch/arm/plat-pxa/
Ddma.c33 pxa_dma_prio prio; member
147 str_prio[dma_channels[chan].prio]); in dbg_show_chan_state()
280 int pxa_request_dma (char *name, pxa_dma_prio prio, in pxa_request_dma() argument
296 if ((dma_channels[i].prio == prio) && in pxa_request_dma()
303 } while (!found && prio--); in pxa_request_dma()
376 dma_channels[i].prio = min((i & 0xf) >> 2, DMA_PRIO_LOW); in pxa_init_dma()
/arch/c6x/include/asm/
Dirq.h51 extern asmlinkage void c6x_do_IRQ(unsigned int prio, struct pt_regs *regs);
/arch/powerpc/platforms/cell/
Dinterrupt.c70 return IIC_IRQ_TYPE_IPI | (bits.prio >> 4); in iic_pending_to_hwnum()
86 out_be64(&iic->regs->prio, iic->eoi_stack[--iic->eoi_ptr]); in iic_eoi()
159 iic->eoi_stack[++iic->eoi_ptr] = pending.prio; in iic_get_irq()
166 out_be64(&__get_cpu_var(cpu_iic).regs->prio, 0xff); in iic_setup_cpu()
308 out_be64(&iic->regs->prio, 0); in init_one_iic()
/arch/arm/plat-mxc/include/mach/
Dirqs.h58 extern int imx_irq_set_priority(unsigned char irq, unsigned char prio);
/arch/unicore32/include/mach/
Ddma.h31 puv3_dma_prio prio,
/arch/xtensa/variants/s6000/include/variant/
Ddmac.h234 int prio, /* 0 (highest) .. 3 (lowest) */ in s6dmac_enable_chan() argument
251 (prio << S6_DMA_CHNCTRL_PRIO) | in s6dmac_enable_chan()
297 int prio, in s6dmac_request_chan() argument
325 s6dmac_enable_chan(dmac, r, prio, periphxfer, in s6dmac_request_chan()
/arch/arm/plat-pxa/include/plat/
Ddma.h79 pxa_dma_prio prio,
/arch/blackfin/mach-common/
Dints-priority.c1167 int ient, prio; in __ipipe_get_irq_priority() local
1175 for (prio = 0; prio <= IVG13-IVG7; prio++) { in __ipipe_get_irq_priority()
1176 if (ivg7_13[prio].ifirst <= ivg && in __ipipe_get_irq_priority()
1177 ivg7_13[prio].istop > ivg) in __ipipe_get_irq_priority()
1178 return IVG7 + prio; in __ipipe_get_irq_priority()
/arch/powerpc/include/asm/
Dcell-regs.h172 u8 prio; member
182 u64 prio; member
Dxics.h47 void (*set_priority)(unsigned char prio);
/arch/s390/include/asm/
Dfcx.h268 u32 prio:8; member

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