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Searched refs:priv2 (Results 1 – 11 of 11) sorted by relevance

/arch/powerpc/platforms/cell/spufs/
Dswitch.c183 struct spu_priv2 __iomem *priv2 = spu->priv2; in save_mfc_cntl() local
188 switch (in_be64(&priv2->mfc_control_RW) & in save_mfc_cntl()
191 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) & in save_mfc_cntl()
197 csa->priv2.mfc_control_RW = in save_mfc_cntl()
198 in_be64(&priv2->mfc_control_RW) | in save_mfc_cntl()
202 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE); in save_mfc_cntl()
203 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) & in save_mfc_cntl()
207 csa->priv2.mfc_control_RW = in save_mfc_cntl()
208 in_be64(&priv2->mfc_control_RW) & in save_mfc_cntl()
263 struct spu_priv2 __iomem *priv2 = spu->priv2; in save_mfc_stopped_status() local
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Dhw_ops.c100 struct spu_priv2 __iomem *priv2 = spu->priv2; in spu_hw_ibox_read() local
106 *data = in_be64(&priv2->puint_mb_R); in spu_hw_ibox_read()
151 struct spu_priv2 __iomem *priv2 = spu->priv2; in spu_hw_signal1_type_set() local
155 tmp = in_be64(&priv2->spu_cfg_RW); in spu_hw_signal1_type_set()
160 out_be64(&priv2->spu_cfg_RW, tmp); in spu_hw_signal1_type_set()
166 return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 1) != 0); in spu_hw_signal1_type_get()
172 struct spu_priv2 __iomem *priv2 = spu->priv2; in spu_hw_signal2_type_set() local
176 tmp = in_be64(&priv2->spu_cfg_RW); in spu_hw_signal2_type_set()
181 out_be64(&priv2->spu_cfg_RW, tmp); in spu_hw_signal2_type_set()
187 return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 2) != 0); in spu_hw_signal2_type_get()
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Dbacking_ops.c138 *data = ctx->csa.priv2.puint_mb_R; in spu_backing_ibox_read()
191 if (ctx->csa.priv2.spu_cfg_RW & 0x1) in spu_backing_signal1_write()
208 if (ctx->csa.priv2.spu_cfg_RW & 0x2) in spu_backing_signal2_write()
222 tmp = ctx->csa.priv2.spu_cfg_RW; in spu_backing_signal1_type_set()
227 ctx->csa.priv2.spu_cfg_RW = tmp; in spu_backing_signal1_type_set()
233 return ((ctx->csa.priv2.spu_cfg_RW & 1) != 0); in spu_backing_signal1_type_get()
241 tmp = ctx->csa.priv2.spu_cfg_RW; in spu_backing_signal2_type_set()
246 ctx->csa.priv2.spu_cfg_RW = tmp; in spu_backing_signal2_type_set()
252 return ((ctx->csa.priv2.spu_cfg_RW & 2) != 0); in spu_backing_signal2_type_get()
277 ctx->csa.priv2.spu_privcntl_RW = val; in spu_backing_privcntl_write()
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Dfile.c1938 ctx->csa.priv2.mfc_control_RW |= MFC_CNTL_DECREMENTER_RUNNING; in spufs_decr_status_set()
1940 ctx->csa.priv2.mfc_control_RW &= ~MFC_CNTL_DECREMENTER_RUNNING; in spufs_decr_status_set()
1948 if (ctx->csa.priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING) in spufs_decr_status_get()
2050 return ctx->csa.priv2.spu_lslr_RW; in spufs_lslr_get()
2135 data = ctx->csa.priv2.puint_mb_R; in __spufs_ibox_info_read()
2216 info.dma_info_type = ctx->csa.priv2.spu_tag_status_query_RW; in __spufs_dma_info_read()
2223 spuqp = &ctx->csa.priv2.spuq[i]; in __spufs_dma_info_read()
2280 puqp = &ctx->csa.priv2.puq[i]; in __spufs_proxydma_info_read()
2638 struct spu_priv2 __iomem *priv2 = spu->priv2; in spufs_show_ctx() local
2641 mfc_control_RW = in_be64(&priv2->mfc_control_RW); in spufs_show_ctx()
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Drun.c103 mfc_cntl = &ctx->spu->priv2->mfc_control_RW; in spu_setup_isolated()
/arch/powerpc/platforms/cell/
Dspu_base.c85 struct spu_priv2 __iomem *priv2 = spu->priv2; in spu_invalidate_slbs() local
90 out_be64(&priv2->slb_invalidate_all_W, 0UL); in spu_invalidate_slbs()
142 struct spu_priv2 __iomem *priv2 = spu->priv2; in spu_restart_dma() local
145 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND); in spu_restart_dma()
154 struct spu_priv2 __iomem *priv2 = spu->priv2; in spu_load_slb() local
159 out_be64(&priv2->slb_index_W, slbe); in spu_load_slb()
161 out_be64(&priv2->slb_esid_RW, 0); in spu_load_slb()
163 out_be64(&priv2->slb_vsid_RW, slb->vsid); in spu_load_slb()
165 out_be64(&priv2->slb_esid_RW, slb->esid); in spu_load_slb()
500 struct spu_priv2 __iomem *priv2; in spu_init_channels() local
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Dspu_manage.c74 iounmap(spu->priv2); in spu_unmap()
159 spu->priv2 = spu_map_prop_old(spu, node, "priv2"); in spu_map_device_old()
160 if (!spu->priv2) in spu_map_device_old()
255 ret = spu_map_resource(spu, 2, (void __iomem**)&spu->priv2, NULL); in spu_map_device()
274 pr_debug(" priv2 : 0x%p\n", spu->priv2); in spu_map_device()
356 spu->priv2, spu->number); in of_create_spu()
/arch/powerpc/platforms/ps3/
Dspu.c135 static void _dump_areas(unsigned int spe_id, unsigned long priv2, in _dump_areas() argument
140 pr_debug("%s:%d: priv2: %lxh\n", func, line, priv2); in _dump_areas()
189 iounmap(spu->priv2); in spu_unmap()
235 spu->priv2 = ioremap(spu_pdata(spu)->priv2_addr, in setup_areas()
238 if (!spu->priv2) { in setup_areas()
246 dump_areas(spu_pdata(spu)->spe_id, (unsigned long)spu->priv2, in setup_areas()
/arch/powerpc/include/asm/
Dspu_csa.h252 struct spu_priv2_collapsed priv2; member
Dspu.h125 struct spu_priv2 __iomem *priv2; member
/arch/powerpc/xmon/
Dxmon.c3074 DUMP_FIELD(spu, "0x%p", priv2); in dump_spu_fields()