| /arch/unicore32/kernel/ |
| D | clock.c | 32 unsigned long rate; member
38 .rate = CLOCK_TICK_RATE,
95 return clk->rate; in clk_get_rate()
100 unsigned long rate; member
104 {.rate = 25175000, .cfg = 0x00002001, .div = 0x9},
105 {.rate = 31500000, .cfg = 0x00002001, .div = 0x7},
106 {.rate = 40000000, .cfg = 0x00003801, .div = 0x9},
107 {.rate = 49500000, .cfg = 0x00003801, .div = 0x7},
108 {.rate = 65000000, .cfg = 0x00002c01, .div = 0x4},
109 {.rate = 78750000, .cfg = 0x00002400, .div = 0x7},
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| /arch/mips/ath79/ |
| D | clock.c | 26 unsigned long rate; member
42 ath79_ref_clk.rate = AR71XX_BASE_FREQ; in ar71xx_clocks_init()
47 freq = div * ath79_ref_clk.rate; in ar71xx_clocks_init()
50 ath79_cpu_clk.rate = freq / div; in ar71xx_clocks_init()
53 ath79_ddr_clk.rate = freq / div; in ar71xx_clocks_init()
56 ath79_ahb_clk.rate = ath79_cpu_clk.rate / div; in ar71xx_clocks_init()
58 ath79_wdt_clk.rate = ath79_ahb_clk.rate; in ar71xx_clocks_init()
59 ath79_uart_clk.rate = ath79_ahb_clk.rate; in ar71xx_clocks_init()
68 ath79_ref_clk.rate = AR724X_BASE_FREQ; in ar724x_clocks_init()
72 freq = div * ath79_ref_clk.rate; in ar724x_clocks_init()
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| /arch/arm/mach-ep93xx/ |
| D | clock.c | 32 unsigned long rate; member
39 int (*set_rate)(struct clk *clk, unsigned long rate);
45 static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
46 static int set_div_rate(struct clk *clk, unsigned long rate);
47 static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate);
48 static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate);
51 .rate = EP93XX_EXT_CLK_RATE,
103 .rate = EP93XX_EXT_CLK_RATE,
107 .rate = EP93XX_EXT_CLK_RATE,
307 unsigned long rate = clk_get_rate(clk->parent); in get_uart_rate() local
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| /arch/arm/mach-omap2/ |
| D | clkt34xx_dpll3m2.c | 50 int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) in omap3_core_dpll_m2_set_rate() argument
60 if (!clk || !rate) in omap3_core_dpll_m2_set_rate()
63 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); in omap3_core_dpll_m2_set_rate()
64 if (validrate != rate) in omap3_core_dpll_m2_set_rate()
67 sdrcrate = sdrc_ick_p->rate; in omap3_core_dpll_m2_set_rate()
68 if (rate > clk->rate) in omap3_core_dpll_m2_set_rate()
69 sdrcrate <<= ((rate / clk->rate) >> 1); in omap3_core_dpll_m2_set_rate()
71 sdrcrate >>= ((clk->rate / rate) >> 1); in omap3_core_dpll_m2_set_rate()
85 _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ; in omap3_core_dpll_m2_set_rate()
93 pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, in omap3_core_dpll_m2_set_rate()
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| D | sdram-nokia.c | 131 long rate; member
143 static unsigned long sdrc_get_fclk_period(long rate) in sdrc_get_fclk_period() argument
146 return 1000000000 / rate; in sdrc_get_fclk_period()
149 static unsigned int sdrc_ps_to_ticks(unsigned int time_ps, long rate) in sdrc_ps_to_ticks() argument
154 tick_ps = sdrc_get_fclk_period(rate); in sdrc_ps_to_ticks()
161 int ticks, long rate, const char *name) in set_sdrc_timing_regval() argument
177 (unsigned int)sdrc_get_fclk_period(rate) * ticks / in set_sdrc_timing_regval()
185 #define SDRC_SET_ONE(reg, st, end, field, rate) \ argument
187 memory_timings->field, (rate), #field) < 0) \
190 #define SDRC_SET_ONE(reg, st, end, field, rate) \ argument
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| D | sdram-qimonda-hyb18m512160af-6.h | 22 .rate = 166000000,
29 .rate = 165941176,
36 .rate = 83000000,
43 .rate = 82970588,
50 .rate = 0
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| D | sdram-micron-mt46h32m32lf-6.h | 23 .rate = 166000000,
30 .rate = 165941176,
37 .rate = 83000000,
44 .rate = 82970588,
51 .rate = 0
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| D | sdram-numonyx-m65kxxxxam.h | 19 .rate = 200000000,
26 .rate = 166000000,
33 .rate = 133000000,
40 .rate = 83000000,
47 .rate = 0
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| D | sdram-hynix-h8mbx00u0mer-0em.h | 19 .rate = 200000000,
26 .rate = 166000000,
33 .rate = 100000000,
40 .rate = 83000000,
47 .rate = 0
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| /arch/powerpc/platforms/512x/ |
| D | clock.c | 43 unsigned long rate; member
87 pr_info(" %s=%ld", p->name, p->rate); in dump_clocks()
90 p->parent->rate); in dump_clocks()
151 return clk->rate; in mpc5121_clk_get_rate()
156 static long mpc5121_clk_round_rate(struct clk *clk, unsigned long rate) in mpc5121_clk_round_rate() argument
158 return rate; in mpc5121_clk_round_rate()
161 static int mpc5121_clk_set_rate(struct clk *clk, unsigned long rate) in mpc5121_clk_set_rate() argument
211 static unsigned long ref_to_sys(unsigned long rate) in ref_to_sys() argument
213 rate *= spmf_mult(); in ref_to_sys()
214 rate *= 2; in ref_to_sys()
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| /arch/arm/mach-pnx4008/ |
| D | clock.c | 36 static int local_set_rate(struct clk *clk, u32 rate);
111 if (!clk->rate) in switch_to_dirty_13mhz()
130 if (!clk->rate) in switch_to_dirty_13mhz()
144 if (!clk->rate) in switch_to_clean_13mhz()
163 if (!clk->rate) in switch_to_clean_13mhz()
194 static int pll160_set_rate(struct clk *clk, u32 rate) in pll160_set_rate() argument
200 parent_rate = clk->parent->rate; in pll160_set_rate()
215 rate -= rate % parent_rate; /*round down the input */ in pll160_set_rate()
217 if (rate > PLL160_MAX_FCCO) in pll160_set_rate()
218 rate = PLL160_MAX_FCCO; in pll160_set_rate()
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| /arch/arm/mach-omap1/ |
| D | clock.c | 56 return clk->parent->rate / div; in omap1_sossi_recalc()
134 static int calc_dsor_exp(struct clk *clk, unsigned long rate) in calc_dsor_exp() argument
155 realrate = parent->rate; in calc_dsor_exp()
157 if (realrate <= rate) in calc_dsor_exp()
171 return clk->parent->rate / dsor; in omap1_ckctl_recalc()
189 return clk->parent->rate / dsor; in omap1_ckctl_recalc_dsp_domain()
193 int omap1_select_table_rate(struct clk *clk, unsigned long rate) in omap1_select_table_rate() argument
199 dpll1_rate = ck_dpll1_p->rate; in omap1_select_table_rate()
200 ref_rate = ck_ref_p->rate; in omap1_select_table_rate()
202 for (ptr = omap1_rate_table; ptr->rate; ptr++) { in omap1_select_table_rate()
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| D | clock.h | 24 extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate);
25 extern int omap1_clk_set_rate(struct clk *clk, unsigned long rate);
27 extern int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
30 extern int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate);
31 extern int omap1_set_uart_rate(struct clk *clk, unsigned long rate);
33 extern int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate);
34 extern long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate);
36 extern int omap1_select_table_rate(struct clk *clk, unsigned long rate);
37 extern long omap1_round_to_table_rate(struct clk *clk, unsigned long rate);
38 extern int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate);
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| /arch/c6x/platforms/ |
| D | pll.c | 81 return clk->rate; in clk_get_rate()
85 long clk_round_rate(struct clk *clk, unsigned long rate) in clk_round_rate() argument
91 return clk->round_rate(clk, rate); in clk_round_rate()
93 return clk->rate; in clk_round_rate()
104 clk->rate = clk->recalc(clk); in propagate_rate()
109 int clk_set_rate(struct clk *clk, unsigned long rate) in clk_set_rate() argument
118 ret = clk->set_rate(clk, rate); in clk_set_rate()
123 clk->rate = clk->recalc(clk); in clk_set_rate()
151 clk->rate = clk->recalc(clk); in clk_set_parent()
164 if (WARN(clk->parent && !clk->parent->rate, in clk_register()
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| /arch/arm/plat-versatile/ |
| D | clock.c | 34 return clk->rate; in clk_get_rate()
38 long clk_round_rate(struct clk *clk, unsigned long rate) in clk_round_rate() argument
42 ret = clk->ops->round(clk, rate); in clk_round_rate()
47 int clk_set_rate(struct clk *clk, unsigned long rate) in clk_set_rate() argument
51 ret = clk->ops->set(clk, rate); in clk_set_rate()
56 long icst_clk_round(struct clk *clk, unsigned long rate) in icst_clk_round() argument
59 vco = icst_hz_to_vco(clk->params, rate); in icst_clk_round()
64 int icst_clk_set(struct clk *clk, unsigned long rate) in icst_clk_set() argument
68 vco = icst_hz_to_vco(clk->params, rate); in icst_clk_set()
69 clk->rate = icst_hz(clk->params, vco); in icst_clk_set()
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| /arch/sh/kernel/cpu/sh4/ |
| D | clock-sh4-202.c | 28 return clk->parent->rate / frqcr3_divisors[idx]; in emi_clk_recalc()
31 static inline int frqcr3_lookup(struct clk *clk, unsigned long rate) in frqcr3_lookup() argument
33 int divisor = clk->parent->rate / rate; in frqcr3_lookup()
56 return clk->parent->rate / frqcr3_divisors[idx]; in femi_clk_recalc()
84 if (clk->ops->set_rate(clk, clk->parent->rate / divisor) == 0) in shoc_clk_init()
94 return clk->parent->rate / frqcr3_divisors[idx]; in shoc_clk_recalc()
97 static int shoc_clk_verify_rate(struct clk *clk, unsigned long rate) in shoc_clk_verify_rate() argument
104 if (rate > bclk_rate) in shoc_clk_verify_rate()
106 if (rate > 66000000) in shoc_clk_verify_rate()
112 static int shoc_clk_set_rate(struct clk *clk, unsigned long rate) in shoc_clk_set_rate() argument
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| /arch/arm/plat-s3c24xx/ |
| D | clock.c | 52 clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON), in s3c24xx_setup_clocks()
53 clk_xtal.rate); in s3c24xx_setup_clocks()
55 clk_mpll.rate = fclk; in s3c24xx_setup_clocks()
56 clk_h.rate = hclk; in s3c24xx_setup_clocks()
57 clk_p.rate = pclk; in s3c24xx_setup_clocks()
58 clk_f.rate = fclk; in s3c24xx_setup_clocks()
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| /arch/arm/mach-highbank/ |
| D | clock.c | 23 unsigned long rate; member
36 return clk->rate; in clk_get_rate()
39 long clk_round_rate(struct clk *clk, unsigned long rate) in clk_round_rate() argument
41 return clk->rate; in clk_round_rate()
44 int clk_set_rate(struct clk *clk, unsigned long rate) in clk_set_rate() argument
49 static struct clk eclk = { .rate = 200000000 };
50 static struct clk pclk = { .rate = 150000000 };
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| /arch/arm/mach-picoxcell/ |
| D | time.c | 21 void __iomem **base, u32 *rate) in timer_get_base_and_rate() argument
28 if (of_property_read_u32(np, "clock-freq", rate)) in timer_get_base_and_rate()
36 u32 irq, rate; in picoxcell_add_clockevent() local
42 timer_get_base_and_rate(event_timer, &iobase, &rate); in picoxcell_add_clockevent()
45 rate); in picoxcell_add_clockevent()
56 u32 rate; in picoxcell_add_clocksource() local
58 timer_get_base_and_rate(source_timer, &iobase, &rate); in picoxcell_add_clocksource()
60 cs = dw_apb_clocksource_init(300, source_timer->name, iobase, rate); in picoxcell_add_clocksource()
83 u32 rate; in picoxcell_init_sched_clock() local
89 timer_get_base_and_rate(sched_timer, &sched_io_base, &rate); in picoxcell_init_sched_clock()
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| /arch/arm/mach-davinci/ |
| D | clock.c | 88 return clk->rate; in clk_get_rate()
92 long clk_round_rate(struct clk *clk, unsigned long rate) in clk_round_rate() argument
98 return clk->round_rate(clk, rate); in clk_round_rate()
100 return clk->rate; in clk_round_rate()
111 clk->rate = clk->recalc(clk); in propagate_rate()
116 int clk_set_rate(struct clk *clk, unsigned long rate) in clk_set_rate() argument
125 ret = clk->set_rate(clk, rate); in clk_set_rate()
130 clk->rate = clk->recalc(clk); in clk_set_rate()
158 clk->rate = clk->recalc(clk); in clk_set_parent()
171 if (WARN(clk->parent && !clk->parent->rate, in clk_register()
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| /arch/arm/plat-spear/ |
| D | clock.c | 222 unsigned long flags, rate; in clk_get_rate() local
225 rate = clk->rate; in clk_get_rate()
228 return rate; in clk_get_rate()
285 int clk_set_rate(struct clk *clk, unsigned long rate) in clk_set_rate() argument
290 if (!clk || !rate) in clk_set_rate()
295 ret = clk->set_rate(clk, rate); in clk_set_rate()
302 ret = clk_set_rate(clk->pclk, mult * rate); in clk_set_rate()
406 round_rate_index(struct clk *clk, unsigned long drate, unsigned long *rate) in round_rate_index() argument
433 *rate = 0; in round_rate_index()
437 *rate = tmp; in round_rate_index()
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| /arch/arm/mach-tegra/ |
| D | tegra2_emc.c | 103 long tegra_emc_round_rate(unsigned long rate) in tegra_emc_round_rate() argument
115 pr_debug("%s: %lu\n", __func__, rate); in tegra_emc_round_rate()
121 rate = rate / 2 / 1000; in tegra_emc_round_rate()
124 if (pdata->tables[i].rate >= rate && in tegra_emc_round_rate()
125 (pdata->tables[i].rate - rate) < distance) { in tegra_emc_round_rate()
126 distance = pdata->tables[i].rate - rate; in tegra_emc_round_rate()
134 pr_debug("%s: using %lu\n", __func__, pdata->tables[best].rate); in tegra_emc_round_rate()
136 return pdata->tables[best].rate * 2 * 1000; in tegra_emc_round_rate()
147 int tegra_emc_set_rate(unsigned long rate) in tegra_emc_set_rate() argument
162 rate = rate / 2 / 1000; in tegra_emc_set_rate()
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| /arch/arm/common/ |
| D | timer-sp.c | 35 long rate; in sp804_get_clock_rate() local
60 rate = clk_get_rate(clk); in sp804_get_clock_rate()
61 if (rate < 0) { in sp804_get_clock_rate()
62 pr_err("sp804: %s clock failed to get rate: %ld\n", name, rate); in sp804_get_clock_rate()
68 return rate; in sp804_get_clock_rate()
82 long rate = sp804_get_clock_rate(name); in __sp804_clocksource_and_sched_clock_init() local
84 if (rate < 0) in __sp804_clocksource_and_sched_clock_init()
95 rate, 200, 32, clocksource_mmio_readl_down); in __sp804_clocksource_and_sched_clock_init()
99 setup_sched_clock(sp804_read, 32, rate); in __sp804_clocksource_and_sched_clock_init()
179 long rate = sp804_get_clock_rate(name); in sp804_clockevents_init() local
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| /arch/mips/kernel/cpufreq/ |
| D | loongson2_clock.c | 45 .rate = 800000000,
81 return (unsigned long)clk->rate; in clk_get_rate()
90 int clk_set_rate(struct clk *clk, unsigned long rate) in clk_set_rate() argument
92 return clk_set_rate_ex(clk, rate, 0); in clk_set_rate()
96 int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id) in clk_set_rate_ex() argument
106 ret = clk->ops->set_rate(clk, rate, algo_id); in clk_set_rate_ex()
118 if (rate == loongson2_clockmod_table[i].frequency) in clk_set_rate_ex()
121 if (rate != loongson2_clockmod_table[i].frequency) in clk_set_rate_ex()
124 clk->rate = rate; in clk_set_rate_ex()
134 long clk_round_rate(struct clk *clk, unsigned long rate) in clk_round_rate() argument
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| /arch/arm/mach-u300/ |
| D | clock.c | 298 static void syscon_clk_rate_set_mclk(unsigned long rate) in syscon_clk_rate_set_mclk() argument
304 switch (rate) { in syscon_clk_rate_set_mclk()
334 rate); in syscon_clk_rate_set_mclk()
345 void syscon_clk_rate_set_cpuclk(unsigned long rate) in syscon_clk_rate_set_cpuclk() argument
350 switch (rate) { in syscon_clk_rate_set_cpuclk()
448 return clk->rate; in clk_get_rate_cpuclk()
469 return clk->rate; in clk_get_rate_ahb_clk()
491 return clk->rate; in clk_get_rate_emif_clk()
514 return clk->rate; in clk_get_rate_xgamclk()
578 return clk->rate; in clk_get_rate_mclk()
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