Home
last modified time | relevance | path

Searched refs:regval (Results 1 – 17 of 17) sorted by relevance

/arch/arm/mach-omap2/
Dam35xx-emac.c42 u32 regval; in am35xx_enable_emac_int() local
44 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); in am35xx_enable_emac_int()
45 regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR | in am35xx_enable_emac_int()
49 omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR); in am35xx_enable_emac_int()
50 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); in am35xx_enable_emac_int()
55 u32 regval; in am35xx_disable_emac_int() local
57 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); in am35xx_disable_emac_int()
58 regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR | in am35xx_disable_emac_int()
60 omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR); in am35xx_disable_emac_int()
61 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); in am35xx_disable_emac_int()
[all …]
Domap_phy_internal.c174 u32 regval; in am35x_musb_reset() local
177 regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); in am35x_musb_reset()
179 regval |= AM35XX_USBOTGSS_SW_RST; in am35x_musb_reset()
180 omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); in am35x_musb_reset()
182 regval &= ~AM35XX_USBOTGSS_SW_RST; in am35x_musb_reset()
183 omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); in am35x_musb_reset()
185 regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); in am35x_musb_reset()
228 u32 regval; in am35x_musb_clear_irq() local
230 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); in am35x_musb_clear_irq()
231 regval |= AM35XX_USBOTGSS_INT_CLR; in am35x_musb_clear_irq()
[all …]
Dgpmc.c460 u32 regval = 0; in gpmc_read_status() local
468 regval = gpmc_read_reg(GPMC_PREFETCH_STATUS); in gpmc_read_status()
469 status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval); in gpmc_read_status()
473 regval = gpmc_read_reg(GPMC_PREFETCH_STATUS); in gpmc_read_status()
474 status = GPMC_PREFETCH_STATUS_COUNT(regval); in gpmc_read_status()
478 regval = gpmc_read_reg(GPMC_STATUS); in gpmc_read_status()
480 status = regval & GPMC_STATUS_BUFF_EMPTY; in gpmc_read_status()
500 u32 regval = 0; in gpmc_cs_configure() local
512 regval = gpmc_read_reg(GPMC_CONFIG); in gpmc_cs_configure()
514 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */ in gpmc_cs_configure()
[all …]
Dsdram-nokia.c160 static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit, in set_sdrc_timing_regval() argument
163 static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit, in set_sdrc_timing_regval()
173 *regval &= ~(mask << st_bit); in set_sdrc_timing_regval()
174 *regval |= ticks << st_bit; in set_sdrc_timing_regval()
197 static int set_sdrc_timing_regval_ps(u32 *regval, int st_bit, int end_bit, in set_sdrc_timing_regval_ps() argument
200 static int set_sdrc_timing_regval_ps(u32 *regval, int st_bit, int end_bit, in set_sdrc_timing_regval_ps()
213 ret = set_sdrc_timing_regval(regval, st_bit, end_bit, ticks, in set_sdrc_timing_regval_ps()
216 ret = set_sdrc_timing_regval(regval, st_bit, end_bit, ticks); in set_sdrc_timing_regval_ps()
/arch/arm/mach-w90x900/
Dgpio.c58 unsigned int regval; in nuc900_gpio_get() local
60 regval = __raw_readl(pio); in nuc900_gpio_get()
61 regval &= GPIO_GPIO(offset); in nuc900_gpio_get()
63 return (regval != 0); in nuc900_gpio_get()
70 unsigned int regval; in nuc900_gpio_set() local
75 regval = __raw_readl(pio); in nuc900_gpio_set()
78 regval |= GPIO_GPIO(offset); in nuc900_gpio_set()
80 regval &= ~GPIO_GPIO(offset); in nuc900_gpio_set()
82 __raw_writel(regval, pio); in nuc900_gpio_set()
91 unsigned int regval; in nuc900_dir_input() local
[all …]
Dirq.c85 unsigned long regval; in nuc900_group_enable() local
87 regval = __raw_readl(REG_AIC_GEN); in nuc900_group_enable()
90 regval |= groupen; in nuc900_group_enable()
92 regval &= ~groupen; in nuc900_group_enable()
94 __raw_writel(regval, REG_AIC_GEN); in nuc900_group_enable()
/arch/sparc/include/asm/
Dturbosparc.h105 static inline void turbosparc_set_ccreg(unsigned long regval) in turbosparc_set_ccreg() argument
109 : "r" (regval), "r" (0x600), "i" (ASI_M_MMUREGS) in turbosparc_set_ccreg()
115 unsigned long regval; in turbosparc_get_ccreg() local
118 : "=r" (regval) in turbosparc_get_ccreg()
120 return regval; in turbosparc_get_ccreg()
Dviking.h145 static inline void viking_set_bpreg(unsigned long regval) in viking_set_bpreg() argument
149 : "r" (regval), "i" (ASI_M_ACTION) in viking_set_bpreg()
155 unsigned long regval; in viking_get_bpreg() local
158 : "=r" (regval) in viking_get_bpreg()
160 return regval; in viking_get_bpreg()
Dpgtsrmmu.h160 static inline void srmmu_set_mmureg(unsigned long regval) in srmmu_set_mmureg() argument
163 "r" (regval), "i" (ASI_M_MMUREGS) : "memory"); in srmmu_set_mmureg()
/arch/sparc/kernel/
Dauxio_32.c86 unsigned char regval; in set_auxio() local
91 regval = sbus_readb(auxio_register); in set_auxio()
92 sbus_writeb(((regval | bits_on) & ~bits_off) | AUXIO_ORMEIN, in set_auxio()
98 regval = sbus_readb(auxio_register); in set_auxio()
99 sbus_writeb(((regval | bits_on) & ~bits_off) | AUXIO_ORMEIN4M, in set_auxio()
Dauxio_64.c34 u8 regval, newval; in __auxio_rmw() local
38 regval = (ebus ? in __auxio_rmw()
41 newval = regval | bits_on; in __auxio_rmw()
/arch/mips/kernel/cpufreq/
Dloongson2_clock.c99 int regval; in clk_set_rate_ex() local
126 regval = LOONGSON_CHIPCFG0; in clk_set_rate_ex()
127 regval = (regval & ~0x7) | (loongson2_clockmod_table[i].index - 1); in clk_set_rate_ex()
128 LOONGSON_CHIPCFG0 = regval; in clk_set_rate_ex()
/arch/arm/mach-omap1/
Dclock.c232 u16 regval; in omap1_clk_set_rate_dsp_domain() local
240 regval = __raw_readw(DSP_CKCTL); in omap1_clk_set_rate_dsp_domain()
241 regval &= ~(3 << clk->rate_offset); in omap1_clk_set_rate_dsp_domain()
242 regval |= dsor_exp << clk->rate_offset; in omap1_clk_set_rate_dsp_domain()
243 __raw_writew(regval, DSP_CKCTL); in omap1_clk_set_rate_dsp_domain()
262 u16 regval; in omap1_clk_set_rate_ckctl_arm() local
270 regval = omap_readw(ARM_CKCTL); in omap1_clk_set_rate_ckctl_arm()
271 regval &= ~(3 << clk->rate_offset); in omap1_clk_set_rate_ckctl_arm()
272 regval |= dsor_exp << clk->rate_offset; in omap1_clk_set_rate_ckctl_arm()
273 regval = verify_ckctl_value(regval); in omap1_clk_set_rate_ckctl_arm()
[all …]
/arch/ia64/sn/kernel/
Dirq.c422 u64 regval; in sn_check_intr() local
441 regval = pcireg_intr_status_get(pcibus_info); in sn_check_intr()
445 regval &= 0xff; in sn_check_intr()
446 if (sn_irq_info->irq_int_bit & regval & in sn_check_intr()
448 regval &= ~(sn_irq_info->irq_int_bit & regval); in sn_check_intr()
453 sn_irq_info->irq_last_intr = regval; in sn_check_intr()
/arch/powerpc/sysdev/bestcomm/
Dbestcomm_priv.h254 u16 regval; in bcom_disable_prefetch() local
256 regval = in_be16(&bcom_eng->regs->PtdCntrl); in bcom_disable_prefetch()
257 out_be16(&bcom_eng->regs->PtdCntrl, regval | 1); in bcom_disable_prefetch()
/arch/arm/mach-lpc32xx/
Dcommon.h64 extern u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval);
Dclock.c208 u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval) in clk_get_pllrate_from_reg() argument
215 if ((regval & LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS) != 0) in clk_get_pllrate_from_reg()
217 if ((regval & LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS) != 0) in clk_get_pllrate_from_reg()
219 if ((regval & LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK) != 0) in clk_get_pllrate_from_reg()
221 pllcfg.pll_m = 1 + ((regval >> 1) & 0xFF); in clk_get_pllrate_from_reg()
222 pllcfg.pll_n = 1 + ((regval >> 9) & 0x3); in clk_get_pllrate_from_reg()
223 pllcfg.pll_p = pll_postdivs[((regval >> 11) & 0x3)]; in clk_get_pllrate_from_reg()