| /arch/arm/mach-imx/ |
| D | clock-imx1.c | 123 return clk->parent->set_rate(clk->parent, rate); in _clk_parent_set_rate()
272 .set_rate = hclk_set_rate,
313 .set_rate = clk48m_set_rate,
433 .set_rate = perclk1_set_rate,
439 .set_rate = perclk2_set_rate,
445 .set_rate = perclk3_set_rate,
471 if (clko_clocks[i]->set_rate && clko_clocks[i]->round_rate) { in clko_set_parent()
472 clk->set_rate = _clk_parent_set_rate; in clko_set_parent()
475 clk->set_rate = NULL; in clko_set_parent()
489 .set_rate = _clk_parent_set_rate,
[all …]
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| /arch/arm/mach-pnx4008/ |
| D | clock.c | 435 .set_rate = &ck_13MHz_set_rate,
460 .set_rate = &pll1_set_rate,
474 .set_rate = &pll160_set_rate,
489 .set_rate = &pll160_set_rate,
503 .set_rate = &pll160_set_rate,
517 .set_rate = &hclk_set_rate,
529 .set_rate = &per_clk_set_rate,
541 .set_rate = &on_off_inv_set_rate,
552 .set_rate = &on_off_set_rate,
563 .set_rate = &on_off_set_rate,
[all …]
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| D | clock.h | 31 int (*set_rate) (struct clk *, u32); member
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| /arch/arm/mach-omap1/ |
| D | clock_data.c | 118 .set_rate = &omap1_set_sossi_rate,
128 .set_rate = omap1_clk_set_rate_ckctl_arm,
142 .set_rate = omap1_clk_set_rate_ckctl_arm,
222 .set_rate = omap1_clk_set_rate_ckctl_arm,
232 .set_rate = omap1_clk_set_rate_ckctl_arm,
244 .set_rate = &omap1_clk_set_rate_dsp_domain,
274 .set_rate = omap1_clk_set_rate_ckctl_arm,
395 .set_rate = omap1_clk_set_rate_ckctl_arm,
409 .set_rate = omap1_clk_set_rate_ckctl_arm,
429 .set_rate = &omap1_set_uart_rate,
[all …]
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| /arch/arm/mach-spear6xx/ |
| D | clock.c | 78 .set_rate = &pll_clk_set_rate,
131 .set_rate = &bus_clk_set_rate,
169 .set_rate = &aux_clk_set_rate,
224 .set_rate = &aux_clk_set_rate,
270 .set_rate = &aux_clk_set_rate,
331 .set_rate = &gpt_clk_set_rate,
393 .set_rate = &gpt_clk_set_rate,
437 .set_rate = &gpt_clk_set_rate,
513 .set_rate = &bus_clk_set_rate,
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| /arch/arm/mach-omap2/ |
| D | clock44xx_data.c | 279 .set_rate = &omap3_noncore_dpll_set_rate,
340 .set_rate = &omap2_clksel_set_rate,
372 .set_rate = &omap2_clksel_set_rate,
395 .set_rate = &omap2_clksel_set_rate,
407 .set_rate = &omap2_clksel_set_rate,
478 .set_rate = &omap2_clksel_set_rate,
508 .set_rate = &omap2_clksel_set_rate,
528 .set_rate = &omap2_clksel_set_rate,
545 .set_rate = &omap2_clksel_set_rate,
570 .set_rate = &omap2_clksel_set_rate,
[all …]
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| /arch/arm/mach-ep93xx/ |
| D | clock.c | 39 int (*set_rate)(struct clk *clk, unsigned long rate); member
99 .set_rate = set_keytchclk_rate,
114 .set_rate = set_div_rate,
121 .set_rate = set_div_rate,
129 .set_rate = set_i2s_sclk_rate,
137 .set_rate = set_i2s_lrclk_rate,
471 if (clk->set_rate) in clk_set_rate()
472 return clk->set_rate(clk, rate); in clk_set_rate()
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| /arch/arm/mach-lpc32xx/ |
| D | clock.h | 28 int (*set_rate) (struct clk *, unsigned long); member
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| /arch/avr32/mach-at32ap/ |
| D | clock.c | 132 if (!clk->set_rate) in clk_round_rate()
136 actual_rate = clk->set_rate(clk, rate, 0); in clk_round_rate()
148 if (!clk->set_rate) in clk_set_rate()
152 ret = clk->set_rate(clk, rate, 1); in clk_set_rate()
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| D | clock.h | 27 long (*set_rate)(struct clk *clk, unsigned long rate, member
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| /arch/arm/mach-spear3xx/ |
| D | clock.c | 79 .set_rate = &pll_clk_set_rate,
132 .set_rate = &bus_clk_set_rate,
170 .set_rate = &aux_clk_set_rate,
216 .set_rate = &aux_clk_set_rate,
277 .set_rate = &gpt_clk_set_rate,
321 .set_rate = &gpt_clk_set_rate,
365 .set_rate = &gpt_clk_set_rate,
433 .set_rate = &bus_clk_set_rate,
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| /arch/arm/mach-mxs/include/mach/ |
| D | clock.h | 44 int (*set_rate) (struct clk *, unsigned long); member
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| /arch/arm/mach-u300/ |
| D | clock.h | 40 int (*set_rate) (struct clk *, unsigned long); member
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| /arch/arm/plat-mxc/include/mach/ |
| D | clock.h | 46 int (*set_rate) (struct clk *, unsigned long); member
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| /arch/arm/mach-prima2/ |
| D | clock.c | 52 int (*set_rate)(struct clk *clk, unsigned long rate); member
155 .set_rate = std_pll_set_rate,
291 .set_rate = cpu_set_rate,
302 .set_rate = dmn_set_rate,
429 if (!clk->ops || !clk->ops->set_rate) in clk_set_rate()
432 return clk->ops->set_rate(clk, rate); in clk_set_rate()
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| /arch/arm/plat-samsung/ |
| D | clock.c | 157 WARN_ON(clk->ops && clk->ops->set_rate == NULL); in clk_set_rate()
159 if (clk->ops == NULL || clk->ops->set_rate == NULL) in clk_set_rate()
163 ret = (clk->ops->set_rate)(clk, rate); in clk_set_rate()
208 .set_rate = clk_default_setrate,
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| /arch/sh/kernel/cpu/sh4/ |
| D | clock-sh4-202.c | 84 if (clk->ops->set_rate(clk, clk->parent->rate / divisor) == 0) in shoc_clk_init()
136 .set_rate = shoc_clk_set_rate,
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| /arch/arm/mach-mxs/ |
| D | clock.c | 160 if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0) in clk_set_rate()
164 ret = clk->set_rate(clk, rate); in clk_set_rate()
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| /arch/mips/include/asm/ |
| D | clock.h | 18 int (*set_rate) (struct clk *clk, unsigned long rate, int algo_id); member
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| /arch/mips/kernel/cpufreq/ |
| D | loongson2_clock.c | 102 if (likely(clk->ops && clk->ops->set_rate)) { in clk_set_rate_ex()
106 ret = clk->ops->set_rate(clk, rate, algo_id); in clk_set_rate_ex()
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| /arch/mips/jz4740/ |
| D | clock.c | 330 .set_rate = jz_clk_main_set_rate,
560 .set_rate = jz_clk_ldclk_set_rate,
576 .set_rate = jz_clk_divided_set_rate,
585 .set_rate = jz_clk_divided_set_rate,
594 .set_rate = jz_clk_divided_set_rate,
656 .set_rate = jz_clk_udc_set_rate,
765 if (!clk->ops->set_rate) in clk_set_rate()
767 return clk->ops->set_rate(clk, rate); in clk_set_rate()
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| D | clock.h | 36 int (*set_rate)(struct clk *clk, unsigned long rate); member
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| /arch/arm/plat-s5p/ |
| D | clock.c | 217 ret = pclk->ops->set_rate(pclk, rate); in s5p_spdif_set_rate()
239 .set_rate = s5p_spdif_set_rate,
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| /arch/arm/mach-msm/ |
| D | clock.h | 39 int (*set_rate)(unsigned id, unsigned rate); member
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| /arch/arm/plat-mxc/ |
| D | clock.c | 150 if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0) in clk_set_rate()
154 ret = clk->set_rate(clk, rate); in clk_set_rate()
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