| /arch/mips/include/asm/ |
| D | war.h | 82 #error Check setting of R4600_V1_INDEX_ICACHEOP_WAR for your platform
112 #error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform
128 #error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform
141 #error Check setting of R5432_CP0_INTERRUPT_WAR for your platform
155 #error Check setting of BCM1250_M3_WAR for your platform
162 #error Check setting of SIBYTE_1956_WAR for your platform
178 #error Check setting of MIPS4K_ICACHE_REFILL_WAR for your platform
197 #error Check setting of MIPS_CACHE_SYNC_WAR for your platform
208 #error Check setting of TX49XX_ICACHE_INDEX_INV_WAR for your platform
216 #error Check setting of RM9000_CDEX_SMP_WAR for your platform
[all …]
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| /arch/arm/mach-msm/ |
| D | gpiomux.c | 29 gpiomux_config_t setting; in msm_gpiomux_write() local
42 setting = cfg->ref ? active : suspended; in msm_gpiomux_write()
43 if (setting & GPIOMUX_VALID) in msm_gpiomux_write()
44 __msm_gpiomux_write(gpio, setting); in msm_gpiomux_write()
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| /arch/mips/include/asm/octeon/ |
| D | cvmx-asxx-defs.h | 88 uint64_t setting:5; member
99 uint64_t setting:5; member
158 uint64_t setting:5; member
201 uint64_t setting:5; member
305 uint64_t setting:5; member
309 uint64_t setting:5; member
320 uint64_t setting:5; member
393 uint64_t setting:5; member
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| /arch/arm/mach-tegra/include/mach/ |
| D | clk.h | 39 int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting);
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| /arch/sh/cchips/ |
| D | Kconfig | 33 The default setting of the HD64461 IRQ is 36.
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| /arch/arm/mach-shmobile/include/mach/ |
| D | head-ap4evb.txt | 81 LIST "Change CPGA setting"
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| D | head-mackerel.txt | 81 LIST "Change CPGA setting"
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| /arch/m32r/kernel/ |
| D | entry.S | 209 ; setting need_resched or sigpending
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| /arch/sparc/mm/ |
| D | tsb.c | 127 #error Broken base page size setting...
141 #error Broken huge page size setting...
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| /arch/m32r/platforms/mappi/ |
| D | dot.gdbinit.nommu | 10 # setting
100 # LCD & CRT dual-head setting (8bpp)
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| D | dot.gdbinit | 10 # setting
100 # LCD & CRT dual-head setting (8bpp)
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| D | dot.gdbinit.smp | 4 # setting
164 # LCD & CRT dual-head setting (8bpp)
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| /arch/unicore32/kernel/ |
| D | head.S | 142 movl r0, #0x201f @ control register setting
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| /arch/mips/kernel/ |
| D | entry.S | 45 # interrupt setting need_resched
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| /arch/frv/kernel/ |
| D | cmode.S | 180 # (15) Release the interrupt mask setting of the MASK register of
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| D | sleep.S | 170 # Release the interrupt mask setting of the MASK register of the
352 # (9) Release the interrupt mask setting of the MASK register of the
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| /arch/arm/mach-tegra/ |
| D | clock.c | 405 int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) in tegra_clk_cfg_ex() argument
416 ret = c->ops->clk_cfg_ex(c, p, setting); in tegra_clk_cfg_ex()
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| D | tegra30_clocks.c | 1111 tegra30_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) in tegra30_plld_clk_cfg_ex() argument
1136 if (setting) in tegra30_plld_clk_cfg_ex()
1650 tegra30_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) in tegra30_vi_clk_cfg_ex() argument
1655 val |= (setting << PERIPH_CLK_VI_SEL_EX_SHIFT) & in tegra30_vi_clk_cfg_ex()
1675 tegra30_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) in tegra30_nand_clk_cfg_ex() argument
1679 if (setting) in tegra30_nand_clk_cfg_ex()
1702 tegra30_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) in tegra30_dtv_clk_cfg_ex() argument
1706 if (setting) in tegra30_dtv_clk_cfg_ex()
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| /arch/mn10300/kernel/ |
| D | entry.S | 113 # make sure we don't miss an interrupt setting need_resched or
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| /arch/m32r/platforms/oaks32r/ |
| D | dot.gdbinit.nommu | 10 # setting
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| /arch/m68k/fpsp040/ |
| D | sgetem.S | 80 fmovel %d0,%fpcr |this fpcr setting is used by the 882
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| /arch/ |
| D | Kconfig | 246 An arch should select this symbol if it supports setting a variable
280 in compatibility mode, supports setting a variable number of bits for
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| /arch/cris/arch-v10/ |
| D | README.mm | 106 The setting of the actual MMU control registers to use this layout would
144 NOTE: while setting up the MMU, we run in a non-mapped mode in the DRAM (0x40
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| /arch/mips/ |
| D | Kconfig.debug | 64 By setting this option to 'Y' you will have your kernel ignore
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| /arch/m32r/platforms/mappi2/ |
| D | dot.gdbinit.vdec2 | 4 # setting
|