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Searched refs:tcfg1 (Results 1 – 3 of 3) sorted by relevance

/arch/arm/plat-samsung/
Dpwm-clock.c175 unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1); in clk_pwm_tdiv_get_rate() local
178 tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id); in clk_pwm_tdiv_get_rate()
179 tcfg1 &= S3C2410_TCFG1_MUX_MASK; in clk_pwm_tdiv_get_rate()
181 if (pwm_cfg_src_is_tclk(tcfg1)) in clk_pwm_tdiv_get_rate()
184 divisor = tcfg_to_divisor(tcfg1); in clk_pwm_tdiv_get_rate()
219 unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1); in clk_pwm_tdiv_update() local
226 tcfg1 = __raw_readl(S3C2410_TCFG1); in clk_pwm_tdiv_update()
227 tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift); in clk_pwm_tdiv_update()
228 tcfg1 |= bits << shift; in clk_pwm_tdiv_update()
229 __raw_writel(tcfg1, S3C2410_TCFG1); in clk_pwm_tdiv_update()
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Dtime.c164 unsigned long tcfg1; in s3c2410_timer_setup() local
176 tcfg1 = __raw_readl(S3C2410_TCFG1); in s3c2410_timer_setup()
177 tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK; in s3c2410_timer_setup()
178 tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1; in s3c2410_timer_setup()
179 __raw_writel(tcfg1, S3C2410_TCFG1); in s3c2410_timer_setup()
210 tcfg1 = __raw_readl(S3C2410_TCFG1); in s3c2410_timer_setup()
217 tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks); in s3c2410_timer_setup()
225 __raw_writel(tcfg1, S3C2410_TCFG1); in s3c2410_timer_setup()
/arch/arm/plat-samsung/include/plat/
Dpwm-clock.h47 static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) in tcfg_to_divisor() argument
50 return 1 << (tcfg1 + 1); in tcfg_to_divisor()
52 return 1 << tcfg1; in tcfg_to_divisor()