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Searched refs:val2 (Results 1 – 22 of 22) sorted by relevance

/arch/sh/boards/mach-dreamcast/
Drtc.c35 unsigned long val1, val2; in aica_rtc_gettimeofday() local
41 val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_gettimeofday()
43 } while (val1 != val2); in aica_rtc_gettimeofday()
59 unsigned long val1, val2; in aica_rtc_settimeofday() local
69 val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_settimeofday()
71 } while (val1 != val2); in aica_rtc_settimeofday()
/arch/arm/kernel/
Dkprobes-test.h231 #define TEST_RR(code1, reg1, val1, code2, reg2, val2, code3) \ argument
234 TEST_ARG_REG(reg2, val2) \
239 #define TEST_RRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\ argument
242 TEST_ARG_REG(reg2, val2) \
248 #define TEST_RRRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4, reg4, val4) \ argument
251 TEST_ARG_REG(reg2, val2) \
265 #define TEST_PR(code1, reg1, val1, code2, reg2, val2, code3) \ argument
268 TEST_ARG_REG(reg2, val2) \
273 #define TEST_RP(code1, reg1, val1, code2, reg2, val2, code3) \ argument
276 TEST_ARG_PTR(reg2, val2) \
[all …]
/arch/mips/pci/
Dops-titan-ht.c108 uint32_t val1, val2, mask; in titan_ht_config_write() local
110 titan_ht_config_read_dword(bus, devfn, offset, &val2); in titan_ht_config_write()
114 val2 &= ~(mask << ((offset & 3) << 8)); in titan_ht_config_write()
116 titan_ht_config_write_dword(bus, devfn, offset, val1 | val2); in titan_ht_config_write()
/arch/ia64/lib/
Dstrlen.S79 #define val2 r23 macro
114 czx1.r val2=w[1] // search 0 byte from right following 8bytes
118 cmp.eq.and p6,p0=8,val2 // p6 = p6 and mask==8
136 tnat.nz.and p7,p0=val2 // test NaT if val2
139 (p8) mov val1=val2 // the other test got us out of the loop
Dstrlen_user.S81 #define val2 r23 macro
117 czx1.r val2=w[1] // search 0 byte from right following 8bytes
121 cmp.eq.and p6,p0=8,val2 // p6 = p6 and mask==8
139 tnat.nz.and p7,p0=val2 // test NaT if val2
142 (p8) mov val1=val2 // val2 contains the value
Dcopy_user.S78 .rotr val1[PIPE_DEPTH],val2[PIPE_DEPTH]
344 EX(.failure_in1,(p8) ld4 val2[0]=[src1],4) // 4-byte aligned
353 EX(.failure_in1,(p9) ld8 val2[1]=[src1],8) // 8-byte aligned
357 EX(.failure_out, (p8) st4 [dst1]=val2[0],4)
361 EX(.failure_out, (p9) st8 [dst1]=val2[1],8)
376 (p16) ld8 val2[0]=[src2],16
379 (EPI) st8 [dst2]=val2[PIPE_DEPTH-1],16
395 EX(.failure_in1,(p8) ld2 val2[0]=[src1],2) // at least 2 bytes
400 EX(.failure_in1,(p9) ld1 val2[1]=[src1]) // only 1 byte left
406 EX(.failure_out, (p8) st2 [dst1]=val2[0],2)
[all …]
/arch/mips/jz4740/
Ddma.c87 uint32_t val2; in jz4740_dma_write_mask() local
88 val2 = jz4740_dma_read(reg); in jz4740_dma_write_mask()
89 val2 &= ~mask; in jz4740_dma_write_mask()
90 val2 |= val; in jz4740_dma_write_mask()
91 jz4740_dma_write(reg, val2); in jz4740_dma_write_mask()
Dclock.c127 uint32_t val2; in jz_clk_reg_write_mask() local
130 val2 = readl(jz_clock_base + reg); in jz_clk_reg_write_mask()
131 val2 &= ~mask; in jz_clk_reg_write_mask()
132 val2 |= val; in jz_clk_reg_write_mask()
133 writel(val2, jz_clock_base + reg); in jz_clk_reg_write_mask()
/arch/alpha/kernel/
Dsys_sable.c111 int port, val1, val2; in sable_ack_irq_hw() local
116 val2 = 0xE0 | 4; in sable_ack_irq_hw()
120 val2 = 0xE0 | 3; in sable_ack_irq_hw()
124 val2 = 0xE0 | 1; in sable_ack_irq_hw()
128 outb(val2, 0x534); /* ack the master */ in sable_ack_irq_hw()
/arch/ia64/include/asm/sn/
Drw_mmr.h26 …n void pio_atomic_phys_write_mmrs(volatile long *mmr1, long val1, volatile long *mmr2, long val2);
/arch/ia64/include/asm/
Dintrinsics.h25 #define ia64_native_set_rr0_to_rr4(val0, val1, val2, val3, val4) \ argument
29 ia64_native_set_rr(0x4000000000000000UL, (val2)); \
Dparavirt_privop.h46 unsigned long val2, unsigned long val3,
414 unsigned long val2, unsigned long val3, in PARAVIRT_DEFINE_CPU_OP1_RET()
419 register unsigned long __val2 asm ("r10") = val2; in PARAVIRT_DEFINE_CPU_OP1_RET()
/arch/x86/include/asm/
Dmsr.h148 #define rdmsr(msr, val1, val2) \ argument
152 (void)((val2) = (u32)(__val >> 32)); \
262 #define write_tsc(val1, val2) wrmsr(MSR_IA32_TSC, (val1), (val2)) argument
Dparavirt.h147 #define rdmsr(msr, val1, val2) \ argument
152 val2 = _l >> 32; \
155 #define wrmsr(msr, val1, val2) \ argument
157 paravirt_write_msr(msr, val1, val2); \
/arch/ia64/include/asm/xen/
Dprivop.h127 unsigned long val2, unsigned long val3,
/arch/powerpc/lib/
Dsstep.c487 unsigned long val1, unsigned long val2, in add_with_carry() argument
490 unsigned long val = val1 + val2; in add_with_carry()
565 unsigned long int val, val2; in emulate_step() local
917 val2 = regs->gpr[rb]; in emulate_step()
922 val2 = (int) val2; in emulate_step()
925 do_cmp_signed(regs, val, val2, rd >> 2); in emulate_step()
930 val2 = regs->gpr[rb]; in emulate_step()
935 val2 = (unsigned int) val2; in emulate_step()
938 do_cmp_unsigned(regs, val, val2, rd >> 2); in emulate_step()
/arch/sparc/kernel/
Dtime_64.c374 unsigned long val2; in hbtick_add_compare() local
380 val2 = __hbird_read_stick() & ~TICKCMP_IRQ_BIT; in hbtick_add_compare()
382 return ((long)(val2 - val)) > 0L; in hbtick_add_compare()
/arch/powerpc/platforms/cell/
Dbeat_wrapper.h43 u64 val0, u64 val1, u64 val2, u64 val3) in beat_set_interrupt_mask() argument
46 val0, val1, val2, val3); in beat_set_interrupt_mask()
/arch/ia64/kernel/
Dparavirt.c131 unsigned long val2, unsigned long val3, in ia64_native_set_rr0_to_rr4_func() argument
134 ia64_native_set_rr0_to_rr4(val0, val1, val2, val3, val4); in ia64_native_set_rr0_to_rr4_func()
378 unsigned long val2, unsigned long val3,
/arch/cris/include/arch-v32/arch/hwregs/iop/
Diop_spu_defs.h124 unsigned int val2 : 5; member
/arch/arm/plat-samsung/
Dadc.c62 unsigned val1, unsigned val2,
/arch/ia64/xen/
Dxen_pv_ops.c685 unsigned long val2, unsigned long val3,