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Searched refs:AR_CH0_DDR_DPLL3 (Results 1 – 2 of 2) sorted by relevance

/drivers/net/wireless/ath/ath9k/
Dreg.h1184 #define AR_CH0_DDR_DPLL3 0x16248 macro
Dhw.c800 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, in ath9k_hw_init_pll()