1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef HW_H
18 #define HW_H
19
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
22 #include <linux/io.h>
23
24 #include "mac.h"
25 #include "ani.h"
26 #include "eeprom.h"
27 #include "calib.h"
28 #include "reg.h"
29 #include "phy.h"
30 #include "btcoex.h"
31
32 #include "../regd.h"
33
34 #define ATHEROS_VENDOR_ID 0x168c
35
36 #define AR5416_DEVID_PCI 0x0023
37 #define AR5416_DEVID_PCIE 0x0024
38 #define AR9160_DEVID_PCI 0x0027
39 #define AR9280_DEVID_PCI 0x0029
40 #define AR9280_DEVID_PCIE 0x002a
41 #define AR9285_DEVID_PCIE 0x002b
42 #define AR2427_DEVID_PCIE 0x002c
43 #define AR9287_DEVID_PCI 0x002d
44 #define AR9287_DEVID_PCIE 0x002e
45 #define AR9300_DEVID_PCIE 0x0030
46 #define AR9300_DEVID_AR9340 0x0031
47 #define AR9300_DEVID_AR9485_PCIE 0x0032
48 #define AR9300_DEVID_AR9580 0x0033
49 #define AR9300_DEVID_AR9462 0x0034
50 #define AR9300_DEVID_AR9330 0x0035
51 #define AR9485_DEVID_AR1111 0x0037
52
53 #define AR5416_AR9100_DEVID 0x000b
54
55 #define AR_SUBVENDOR_ID_NOG 0x0e11
56 #define AR_SUBVENDOR_ID_NEW_A 0x7065
57 #define AR5416_MAGIC 0x19641014
58
59 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
60 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
61 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
62
63 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
64
65 #define ATH_DEFAULT_NOISE_FLOOR -95
66
67 #define ATH9K_RSSI_BAD -128
68
69 #define ATH9K_NUM_CHANNELS 38
70
71 /* Register read/write primitives */
72 #define REG_WRITE(_ah, _reg, _val) \
73 (_ah)->reg_ops.write((_ah), (_val), (_reg))
74
75 #define REG_READ(_ah, _reg) \
76 (_ah)->reg_ops.read((_ah), (_reg))
77
78 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
79 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
80
81 #define REG_RMW(_ah, _reg, _set, _clr) \
82 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
83
84 #define ENABLE_REGWRITE_BUFFER(_ah) \
85 do { \
86 if ((_ah)->reg_ops.enable_write_buffer) \
87 (_ah)->reg_ops.enable_write_buffer((_ah)); \
88 } while (0)
89
90 #define REGWRITE_BUFFER_FLUSH(_ah) \
91 do { \
92 if ((_ah)->reg_ops.write_flush) \
93 (_ah)->reg_ops.write_flush((_ah)); \
94 } while (0)
95
96 #define PR_EEP(_s, _val) \
97 do { \
98 len += snprintf(buf + len, size - len, "%20s : %10d\n", \
99 _s, (_val)); \
100 } while (0)
101
102 #define SM(_v, _f) (((_v) << _f##_S) & _f)
103 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
104 #define REG_RMW_FIELD(_a, _r, _f, _v) \
105 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
106 #define REG_READ_FIELD(_a, _r, _f) \
107 (((REG_READ(_a, _r) & _f) >> _f##_S))
108 #define REG_SET_BIT(_a, _r, _f) \
109 REG_RMW(_a, _r, (_f), 0)
110 #define REG_CLR_BIT(_a, _r, _f) \
111 REG_RMW(_a, _r, 0, (_f))
112
113 #define DO_DELAY(x) do { \
114 if (((++(x) % 64) == 0) && \
115 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
116 != ATH_USB)) \
117 udelay(1); \
118 } while (0)
119
120 #define REG_WRITE_ARRAY(iniarray, column, regWr) \
121 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
122
123 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
124 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
125 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
126 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
127 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
128 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
129 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
130 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16
131 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17
132 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18
133 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19
134 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14
135 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13
136 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9
137 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8
138 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d
139 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e
140
141 #define AR_GPIOD_MASK 0x00001FFF
142 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
143
144 #define BASE_ACTIVATE_DELAY 100
145 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100)
146 #define COEF_SCALE_S 24
147 #define HT40_CHANNEL_CENTER_SHIFT 10
148
149 #define ATH9K_ANTENNA0_CHAINMASK 0x1
150 #define ATH9K_ANTENNA1_CHAINMASK 0x2
151
152 #define ATH9K_NUM_DMA_DEBUG_REGS 8
153 #define ATH9K_NUM_QUEUES 10
154
155 #define MAX_RATE_POWER 63
156 #define AH_WAIT_TIMEOUT 100000 /* (us) */
157 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
158 #define AH_TIME_QUANTUM 10
159 #define AR_KEYTABLE_SIZE 128
160 #define POWER_UP_TIME 10000
161 #define SPUR_RSSI_THRESH 40
162 #define UPPER_5G_SUB_BAND_START 5700
163 #define MID_5G_SUB_BAND_START 5400
164
165 #define CAB_TIMEOUT_VAL 10
166 #define BEACON_TIMEOUT_VAL 10
167 #define MIN_BEACON_TIMEOUT_VAL 1
168 #define SLEEP_SLOP 3
169
170 #define INIT_CONFIG_STATUS 0x00000000
171 #define INIT_RSSI_THR 0x00000700
172 #define INIT_BCON_CNTRL_REG 0x00000000
173
174 #define TU_TO_USEC(_tu) ((_tu) << 10)
175
176 #define ATH9K_HW_RX_HP_QDEPTH 16
177 #define ATH9K_HW_RX_LP_QDEPTH 128
178
179 #define PAPRD_GAIN_TABLE_ENTRIES 32
180 #define PAPRD_TABLE_SZ 24
181 #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0
182
183 enum ath_hw_txq_subtype {
184 ATH_TXQ_AC_BE = 0,
185 ATH_TXQ_AC_BK = 1,
186 ATH_TXQ_AC_VI = 2,
187 ATH_TXQ_AC_VO = 3,
188 };
189
190 enum ath_ini_subsys {
191 ATH_INI_PRE = 0,
192 ATH_INI_CORE,
193 ATH_INI_POST,
194 ATH_INI_NUM_SPLIT,
195 };
196
197 enum ath9k_hw_caps {
198 ATH9K_HW_CAP_HT = BIT(0),
199 ATH9K_HW_CAP_RFSILENT = BIT(1),
200 ATH9K_HW_CAP_AUTOSLEEP = BIT(2),
201 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3),
202 ATH9K_HW_CAP_EDMA = BIT(4),
203 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5),
204 ATH9K_HW_CAP_LDPC = BIT(6),
205 ATH9K_HW_CAP_FASTCLOCK = BIT(7),
206 ATH9K_HW_CAP_SGI_20 = BIT(8),
207 ATH9K_HW_CAP_PAPRD = BIT(9),
208 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10),
209 ATH9K_HW_CAP_2GHZ = BIT(11),
210 ATH9K_HW_CAP_5GHZ = BIT(12),
211 ATH9K_HW_CAP_APM = BIT(13),
212 ATH9K_HW_CAP_RTT = BIT(14),
213 ATH9K_HW_CAP_MCI = BIT(15),
214 ATH9K_HW_CAP_DFS = BIT(16),
215 };
216
217 struct ath9k_hw_capabilities {
218 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
219 u16 rts_aggr_limit;
220 u8 tx_chainmask;
221 u8 rx_chainmask;
222 u8 max_txchains;
223 u8 max_rxchains;
224 u8 num_gpio_pins;
225 u8 rx_hp_qdepth;
226 u8 rx_lp_qdepth;
227 u8 rx_status_len;
228 u8 tx_desc_len;
229 u8 txs_len;
230 u16 pcie_lcr_offset;
231 bool pcie_lcr_extsync_en;
232 };
233
234 struct ath9k_ops_config {
235 int dma_beacon_response_time;
236 int sw_beacon_response_time;
237 int additional_swba_backoff;
238 int ack_6mb;
239 u32 cwm_ignore_extcca;
240 bool pcieSerDesWrite;
241 u8 pcie_clock_req;
242 u32 pcie_waen;
243 u8 analog_shiftreg;
244 u8 paprd_disable;
245 u32 ofdm_trig_low;
246 u32 ofdm_trig_high;
247 u32 cck_trig_high;
248 u32 cck_trig_low;
249 u32 enable_ani;
250 int serialize_regmode;
251 bool rx_intr_mitigation;
252 bool tx_intr_mitigation;
253 #define SPUR_DISABLE 0
254 #define SPUR_ENABLE_IOCTL 1
255 #define SPUR_ENABLE_EEPROM 2
256 #define AR_SPUR_5413_1 1640
257 #define AR_SPUR_5413_2 1200
258 #define AR_NO_SPUR 0x8000
259 #define AR_BASE_FREQ_2GHZ 2300
260 #define AR_BASE_FREQ_5GHZ 4900
261 #define AR_SPUR_FEEQ_BOUND_HT40 19
262 #define AR_SPUR_FEEQ_BOUND_HT20 10
263 int spurmode;
264 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
265 u8 max_txtrig_level;
266 u16 ani_poll_interval; /* ANI poll interval in ms */
267 };
268
269 enum ath9k_int {
270 ATH9K_INT_RX = 0x00000001,
271 ATH9K_INT_RXDESC = 0x00000002,
272 ATH9K_INT_RXHP = 0x00000001,
273 ATH9K_INT_RXLP = 0x00000002,
274 ATH9K_INT_RXNOFRM = 0x00000008,
275 ATH9K_INT_RXEOL = 0x00000010,
276 ATH9K_INT_RXORN = 0x00000020,
277 ATH9K_INT_TX = 0x00000040,
278 ATH9K_INT_TXDESC = 0x00000080,
279 ATH9K_INT_TIM_TIMER = 0x00000100,
280 ATH9K_INT_MCI = 0x00000200,
281 ATH9K_INT_BB_WATCHDOG = 0x00000400,
282 ATH9K_INT_TXURN = 0x00000800,
283 ATH9K_INT_MIB = 0x00001000,
284 ATH9K_INT_RXPHY = 0x00004000,
285 ATH9K_INT_RXKCM = 0x00008000,
286 ATH9K_INT_SWBA = 0x00010000,
287 ATH9K_INT_BMISS = 0x00040000,
288 ATH9K_INT_BNR = 0x00100000,
289 ATH9K_INT_TIM = 0x00200000,
290 ATH9K_INT_DTIM = 0x00400000,
291 ATH9K_INT_DTIMSYNC = 0x00800000,
292 ATH9K_INT_GPIO = 0x01000000,
293 ATH9K_INT_CABEND = 0x02000000,
294 ATH9K_INT_TSFOOR = 0x04000000,
295 ATH9K_INT_GENTIMER = 0x08000000,
296 ATH9K_INT_CST = 0x10000000,
297 ATH9K_INT_GTT = 0x20000000,
298 ATH9K_INT_FATAL = 0x40000000,
299 ATH9K_INT_GLOBAL = 0x80000000,
300 ATH9K_INT_BMISC = ATH9K_INT_TIM |
301 ATH9K_INT_DTIM |
302 ATH9K_INT_DTIMSYNC |
303 ATH9K_INT_TSFOOR |
304 ATH9K_INT_CABEND,
305 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
306 ATH9K_INT_RXDESC |
307 ATH9K_INT_RXEOL |
308 ATH9K_INT_RXORN |
309 ATH9K_INT_TXURN |
310 ATH9K_INT_TXDESC |
311 ATH9K_INT_MIB |
312 ATH9K_INT_RXPHY |
313 ATH9K_INT_RXKCM |
314 ATH9K_INT_SWBA |
315 ATH9K_INT_BMISS |
316 ATH9K_INT_GPIO,
317 ATH9K_INT_NOCARD = 0xffffffff
318 };
319
320 #define CHANNEL_CW_INT 0x00002
321 #define CHANNEL_CCK 0x00020
322 #define CHANNEL_OFDM 0x00040
323 #define CHANNEL_2GHZ 0x00080
324 #define CHANNEL_5GHZ 0x00100
325 #define CHANNEL_PASSIVE 0x00200
326 #define CHANNEL_DYN 0x00400
327 #define CHANNEL_HALF 0x04000
328 #define CHANNEL_QUARTER 0x08000
329 #define CHANNEL_HT20 0x10000
330 #define CHANNEL_HT40PLUS 0x20000
331 #define CHANNEL_HT40MINUS 0x40000
332
333 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
334 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
335 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
336 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
337 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
338 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
339 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
340 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
341 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
342 #define CHANNEL_ALL \
343 (CHANNEL_OFDM| \
344 CHANNEL_CCK| \
345 CHANNEL_2GHZ | \
346 CHANNEL_5GHZ | \
347 CHANNEL_HT20 | \
348 CHANNEL_HT40PLUS | \
349 CHANNEL_HT40MINUS)
350
351 #define MAX_RTT_TABLE_ENTRY 6
352 #define RTT_HIST_MAX 3
353 struct ath9k_rtt_hist {
354 u32 table[AR9300_MAX_CHAINS][RTT_HIST_MAX][MAX_RTT_TABLE_ENTRY];
355 u8 num_readings;
356 };
357
358 #define MAX_IQCAL_MEASUREMENT 8
359 #define MAX_CL_TAB_ENTRY 16
360
361 struct ath9k_hw_cal_data {
362 u16 channel;
363 u32 channelFlags;
364 int32_t CalValid;
365 int8_t iCoff;
366 int8_t qCoff;
367 bool paprd_done;
368 bool nfcal_pending;
369 bool nfcal_interference;
370 bool done_txiqcal_once;
371 bool done_txclcal_once;
372 u16 small_signal_gain[AR9300_MAX_CHAINS];
373 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
374 u32 num_measures[AR9300_MAX_CHAINS];
375 int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS];
376 u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY];
377 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
378 struct ath9k_rtt_hist rtt_hist;
379 };
380
381 struct ath9k_channel {
382 struct ieee80211_channel *chan;
383 struct ar5416AniState ani;
384 u16 channel;
385 u32 channelFlags;
386 u32 chanmode;
387 s16 noisefloor;
388 };
389
390 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
391 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
392 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
393 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
394 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
395 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
396 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
397 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
398 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
399 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
400 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
401 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
402
403 /* These macros check chanmode and not channelFlags */
404 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
405 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
406 ((_c)->chanmode == CHANNEL_G_HT20))
407 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
408 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
409 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
410 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
411 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
412
413 enum ath9k_power_mode {
414 ATH9K_PM_AWAKE = 0,
415 ATH9K_PM_FULL_SLEEP,
416 ATH9K_PM_NETWORK_SLEEP,
417 ATH9K_PM_UNDEFINED
418 };
419
420 enum ser_reg_mode {
421 SER_REG_MODE_OFF = 0,
422 SER_REG_MODE_ON = 1,
423 SER_REG_MODE_AUTO = 2,
424 };
425
426 enum ath9k_rx_qtype {
427 ATH9K_RX_QUEUE_HP,
428 ATH9K_RX_QUEUE_LP,
429 ATH9K_RX_QUEUE_MAX,
430 };
431
432 struct ath9k_beacon_state {
433 u32 bs_nexttbtt;
434 u32 bs_nextdtim;
435 u32 bs_intval;
436 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
437 u32 bs_dtimperiod;
438 u16 bs_cfpperiod;
439 u16 bs_cfpmaxduration;
440 u32 bs_cfpnext;
441 u16 bs_timoffset;
442 u16 bs_bmissthreshold;
443 u32 bs_sleepduration;
444 u32 bs_tsfoor_threshold;
445 };
446
447 struct chan_centers {
448 u16 synth_center;
449 u16 ctl_center;
450 u16 ext_center;
451 };
452
453 enum {
454 ATH9K_RESET_POWER_ON,
455 ATH9K_RESET_WARM,
456 ATH9K_RESET_COLD,
457 };
458
459 struct ath9k_hw_version {
460 u32 magic;
461 u16 devid;
462 u16 subvendorid;
463 u32 macVersion;
464 u16 macRev;
465 u16 phyRev;
466 u16 analog5GhzRev;
467 u16 analog2GhzRev;
468 enum ath_usb_dev usbdev;
469 };
470
471 /* Generic TSF timer definitions */
472
473 #define ATH_MAX_GEN_TIMER 16
474
475 #define AR_GENTMR_BIT(_index) (1 << (_index))
476
477 /*
478 * Using de Bruijin sequence to look up 1's index in a 32 bit number
479 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
480 */
481 #define debruijn32 0x077CB531U
482
483 struct ath_gen_timer_configuration {
484 u32 next_addr;
485 u32 period_addr;
486 u32 mode_addr;
487 u32 mode_mask;
488 };
489
490 struct ath_gen_timer {
491 void (*trigger)(void *arg);
492 void (*overflow)(void *arg);
493 void *arg;
494 u8 index;
495 };
496
497 struct ath_gen_timer_table {
498 u32 gen_timer_index[32];
499 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
500 union {
501 unsigned long timer_bits;
502 u16 val;
503 } timer_mask;
504 };
505
506 struct ath_hw_antcomb_conf {
507 u8 main_lna_conf;
508 u8 alt_lna_conf;
509 u8 fast_div_bias;
510 u8 main_gaintb;
511 u8 alt_gaintb;
512 int lna1_lna2_delta;
513 u8 div_group;
514 };
515
516 /**
517 * struct ath_hw_radar_conf - radar detection initialization parameters
518 *
519 * @pulse_inband: threshold for checking the ratio of in-band power
520 * to total power for short radar pulses (half dB steps)
521 * @pulse_inband_step: threshold for checking an in-band power to total
522 * power ratio increase for short radar pulses (half dB steps)
523 * @pulse_height: threshold for detecting the beginning of a short
524 * radar pulse (dB step)
525 * @pulse_rssi: threshold for detecting if a short radar pulse is
526 * gone (dB step)
527 * @pulse_maxlen: maximum pulse length (0.8 us steps)
528 *
529 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
530 * @radar_inband: threshold for checking the ratio of in-band power
531 * to total power for long radar pulses (half dB steps)
532 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
533 *
534 * @ext_channel: enable extension channel radar detection
535 */
536 struct ath_hw_radar_conf {
537 unsigned int pulse_inband;
538 unsigned int pulse_inband_step;
539 unsigned int pulse_height;
540 unsigned int pulse_rssi;
541 unsigned int pulse_maxlen;
542
543 unsigned int radar_rssi;
544 unsigned int radar_inband;
545 int fir_power;
546
547 bool ext_channel;
548 };
549
550 /**
551 * struct ath_hw_private_ops - callbacks used internally by hardware code
552 *
553 * This structure contains private callbacks designed to only be used internally
554 * by the hardware core.
555 *
556 * @init_cal_settings: setup types of calibrations supported
557 * @init_cal: starts actual calibration
558 *
559 * @init_mode_regs: Initializes mode registers
560 * @init_mode_gain_regs: Initialize TX/RX gain registers
561 *
562 * @rf_set_freq: change frequency
563 * @spur_mitigate_freq: spur mitigation
564 * @rf_alloc_ext_banks:
565 * @rf_free_ext_banks:
566 * @set_rf_regs:
567 * @compute_pll_control: compute the PLL control value to use for
568 * AR_RTC_PLL_CONTROL for a given channel
569 * @setup_calibration: set up calibration
570 * @iscal_supported: used to query if a type of calibration is supported
571 *
572 * @ani_cache_ini_regs: cache the values for ANI from the initial
573 * register settings through the register initialization.
574 */
575 struct ath_hw_private_ops {
576 /* Calibration ops */
577 void (*init_cal_settings)(struct ath_hw *ah);
578 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
579
580 void (*init_mode_regs)(struct ath_hw *ah);
581 void (*init_mode_gain_regs)(struct ath_hw *ah);
582 void (*setup_calibration)(struct ath_hw *ah,
583 struct ath9k_cal_list *currCal);
584
585 /* PHY ops */
586 int (*rf_set_freq)(struct ath_hw *ah,
587 struct ath9k_channel *chan);
588 void (*spur_mitigate_freq)(struct ath_hw *ah,
589 struct ath9k_channel *chan);
590 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
591 void (*rf_free_ext_banks)(struct ath_hw *ah);
592 bool (*set_rf_regs)(struct ath_hw *ah,
593 struct ath9k_channel *chan,
594 u16 modesIndex);
595 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
596 void (*init_bb)(struct ath_hw *ah,
597 struct ath9k_channel *chan);
598 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
599 void (*olc_init)(struct ath_hw *ah);
600 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
601 void (*mark_phy_inactive)(struct ath_hw *ah);
602 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
603 bool (*rfbus_req)(struct ath_hw *ah);
604 void (*rfbus_done)(struct ath_hw *ah);
605 void (*restore_chainmask)(struct ath_hw *ah);
606 u32 (*compute_pll_control)(struct ath_hw *ah,
607 struct ath9k_channel *chan);
608 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
609 int param);
610 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
611 void (*set_radar_params)(struct ath_hw *ah,
612 struct ath_hw_radar_conf *conf);
613 int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan,
614 u8 *ini_reloaded);
615
616 /* ANI */
617 void (*ani_cache_ini_regs)(struct ath_hw *ah);
618 };
619
620 /**
621 * struct ath_hw_ops - callbacks used by hardware code and driver code
622 *
623 * This structure contains callbacks designed to to be used internally by
624 * hardware code and also by the lower level driver.
625 *
626 * @config_pci_powersave:
627 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
628 */
629 struct ath_hw_ops {
630 void (*config_pci_powersave)(struct ath_hw *ah,
631 bool power_off);
632 void (*rx_enable)(struct ath_hw *ah);
633 void (*set_desc_link)(void *ds, u32 link);
634 bool (*calibrate)(struct ath_hw *ah,
635 struct ath9k_channel *chan,
636 u8 rxchainmask,
637 bool longcal);
638 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
639 void (*set_txdesc)(struct ath_hw *ah, void *ds,
640 struct ath_tx_info *i);
641 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
642 struct ath_tx_status *ts);
643 void (*antdiv_comb_conf_get)(struct ath_hw *ah,
644 struct ath_hw_antcomb_conf *antconf);
645 void (*antdiv_comb_conf_set)(struct ath_hw *ah,
646 struct ath_hw_antcomb_conf *antconf);
647
648 };
649
650 struct ath_nf_limits {
651 s16 max;
652 s16 min;
653 s16 nominal;
654 };
655
656 enum ath_cal_list {
657 TX_IQ_CAL = BIT(0),
658 TX_IQ_ON_AGC_CAL = BIT(1),
659 TX_CL_CAL = BIT(2),
660 };
661
662 /* ah_flags */
663 #define AH_USE_EEPROM 0x1
664 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
665 #define AH_FASTCC 0x4
666
667 struct ath_hw {
668 struct ath_ops reg_ops;
669
670 struct ieee80211_hw *hw;
671 struct ath_common common;
672 struct ath9k_hw_version hw_version;
673 struct ath9k_ops_config config;
674 struct ath9k_hw_capabilities caps;
675 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
676 struct ath9k_channel *curchan;
677
678 union {
679 struct ar5416_eeprom_def def;
680 struct ar5416_eeprom_4k map4k;
681 struct ar9287_eeprom map9287;
682 struct ar9300_eeprom ar9300_eep;
683 } eeprom;
684 const struct eeprom_ops *eep_ops;
685
686 bool sw_mgmt_crypto;
687 bool is_pciexpress;
688 bool aspm_enabled;
689 bool is_monitoring;
690 bool need_an_top2_fixup;
691 u16 tx_trig_level;
692
693 u32 nf_regs[6];
694 struct ath_nf_limits nf_2g;
695 struct ath_nf_limits nf_5g;
696 u16 rfsilent;
697 u32 rfkill_gpio;
698 u32 rfkill_polarity;
699 u32 ah_flags;
700
701 bool htc_reset_init;
702
703 enum nl80211_iftype opmode;
704 enum ath9k_power_mode power_mode;
705
706 s8 noise;
707 struct ath9k_hw_cal_data *caldata;
708 struct ath9k_pacal_info pacal_info;
709 struct ar5416Stats stats;
710 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
711
712 int16_t curchan_rad_index;
713 enum ath9k_int imask;
714 u32 imrs2_reg;
715 u32 txok_interrupt_mask;
716 u32 txerr_interrupt_mask;
717 u32 txdesc_interrupt_mask;
718 u32 txeol_interrupt_mask;
719 u32 txurn_interrupt_mask;
720 atomic_t intr_ref_cnt;
721 bool chip_fullsleep;
722 u32 atim_window;
723 u32 modes_index;
724
725 /* Calibration */
726 u32 supp_cals;
727 struct ath9k_cal_list iq_caldata;
728 struct ath9k_cal_list adcgain_caldata;
729 struct ath9k_cal_list adcdc_caldata;
730 struct ath9k_cal_list tempCompCalData;
731 struct ath9k_cal_list *cal_list;
732 struct ath9k_cal_list *cal_list_last;
733 struct ath9k_cal_list *cal_list_curr;
734 #define totalPowerMeasI meas0.unsign
735 #define totalPowerMeasQ meas1.unsign
736 #define totalIqCorrMeas meas2.sign
737 #define totalAdcIOddPhase meas0.unsign
738 #define totalAdcIEvenPhase meas1.unsign
739 #define totalAdcQOddPhase meas2.unsign
740 #define totalAdcQEvenPhase meas3.unsign
741 #define totalAdcDcOffsetIOddPhase meas0.sign
742 #define totalAdcDcOffsetIEvenPhase meas1.sign
743 #define totalAdcDcOffsetQOddPhase meas2.sign
744 #define totalAdcDcOffsetQEvenPhase meas3.sign
745 union {
746 u32 unsign[AR5416_MAX_CHAINS];
747 int32_t sign[AR5416_MAX_CHAINS];
748 } meas0;
749 union {
750 u32 unsign[AR5416_MAX_CHAINS];
751 int32_t sign[AR5416_MAX_CHAINS];
752 } meas1;
753 union {
754 u32 unsign[AR5416_MAX_CHAINS];
755 int32_t sign[AR5416_MAX_CHAINS];
756 } meas2;
757 union {
758 u32 unsign[AR5416_MAX_CHAINS];
759 int32_t sign[AR5416_MAX_CHAINS];
760 } meas3;
761 u16 cal_samples;
762 u8 enabled_cals;
763
764 u32 sta_id1_defaults;
765 u32 misc_mode;
766 enum {
767 AUTO_32KHZ,
768 USE_32KHZ,
769 DONT_USE_32KHZ,
770 } enable_32kHz_clock;
771
772 /* Private to hardware code */
773 struct ath_hw_private_ops private_ops;
774 /* Accessed by the lower level driver */
775 struct ath_hw_ops ops;
776
777 /* Used to program the radio on non single-chip devices */
778 u32 *analogBank0Data;
779 u32 *analogBank1Data;
780 u32 *analogBank2Data;
781 u32 *analogBank3Data;
782 u32 *analogBank6Data;
783 u32 *analogBank6TPCData;
784 u32 *analogBank7Data;
785 u32 *bank6Temp;
786
787 u8 txpower_limit;
788 int coverage_class;
789 u32 slottime;
790 u32 globaltxtimeout;
791
792 /* ANI */
793 u32 proc_phyerr;
794 u32 aniperiod;
795 int totalSizeDesired[5];
796 int coarse_high[5];
797 int coarse_low[5];
798 int firpwr[5];
799 enum ath9k_ani_cmd ani_function;
800
801 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
802 struct ath_btcoex_hw btcoex_hw;
803 #endif
804
805 u32 intr_txqs;
806 u8 txchainmask;
807 u8 rxchainmask;
808
809 struct ath_hw_radar_conf radar_conf;
810
811 u32 originalGain[22];
812 int initPDADC;
813 int PDADCdelta;
814 int led_pin;
815 u32 gpio_mask;
816 u32 gpio_val;
817
818 struct ar5416IniArray iniModes;
819 struct ar5416IniArray iniCommon;
820 struct ar5416IniArray iniBank0;
821 struct ar5416IniArray iniBB_RfGain;
822 struct ar5416IniArray iniBank1;
823 struct ar5416IniArray iniBank2;
824 struct ar5416IniArray iniBank3;
825 struct ar5416IniArray iniBank6;
826 struct ar5416IniArray iniBank6TPC;
827 struct ar5416IniArray iniBank7;
828 struct ar5416IniArray iniAddac;
829 struct ar5416IniArray iniPcieSerdes;
830 struct ar5416IniArray iniPcieSerdesLowPower;
831 struct ar5416IniArray iniModesFastClock;
832 struct ar5416IniArray iniAdditional;
833 struct ar5416IniArray iniModesRxGain;
834 struct ar5416IniArray iniModesTxGain;
835 struct ar5416IniArray iniCckfirNormal;
836 struct ar5416IniArray iniCckfirJapan2484;
837 struct ar5416IniArray ini_japan2484;
838 struct ar5416IniArray iniModes_9271_ANI_reg;
839 struct ar5416IniArray ini_radio_post_sys2ant;
840 struct ar5416IniArray ini_BTCOEX_MAX_TXPWR;
841
842 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
843 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
844 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
845 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
846
847 u32 intr_gen_timer_trigger;
848 u32 intr_gen_timer_thresh;
849 struct ath_gen_timer_table hw_gen_timers;
850
851 struct ar9003_txs *ts_ring;
852 void *ts_start;
853 u32 ts_paddr_start;
854 u32 ts_paddr_end;
855 u16 ts_tail;
856 u16 ts_size;
857
858 u32 bb_watchdog_last_status;
859 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
860 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */
861
862 unsigned int paprd_target_power;
863 unsigned int paprd_training_power;
864 unsigned int paprd_ratemask;
865 unsigned int paprd_ratemask_ht40;
866 bool paprd_table_write_done;
867 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
868 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
869 /*
870 * Store the permanent value of Reg 0x4004in WARegVal
871 * so we dont have to R/M/W. We should not be reading
872 * this register when in sleep states.
873 */
874 u32 WARegVal;
875
876 /* Enterprise mode cap */
877 u32 ent_mode;
878
879 bool is_clk_25mhz;
880 int (*get_mac_revision)(void);
881 int (*external_reset)(void);
882 };
883
884 struct ath_bus_ops {
885 enum ath_bus_type ath_bus_type;
886 void (*read_cachesize)(struct ath_common *common, int *csz);
887 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
888 void (*bt_coex_prep)(struct ath_common *common);
889 void (*extn_synch_en)(struct ath_common *common);
890 void (*aspm_init)(struct ath_common *common);
891 };
892
ath9k_hw_common(struct ath_hw * ah)893 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
894 {
895 return &ah->common;
896 }
897
ath9k_hw_regulatory(struct ath_hw * ah)898 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
899 {
900 return &(ath9k_hw_common(ah)->regulatory);
901 }
902
ath9k_hw_private_ops(struct ath_hw * ah)903 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
904 {
905 return &ah->private_ops;
906 }
907
ath9k_hw_ops(struct ath_hw * ah)908 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
909 {
910 return &ah->ops;
911 }
912
get_streams(int mask)913 static inline u8 get_streams(int mask)
914 {
915 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
916 }
917
918 /* Initialization, Detach, Reset */
919 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
920 void ath9k_hw_deinit(struct ath_hw *ah);
921 int ath9k_hw_init(struct ath_hw *ah);
922 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
923 struct ath9k_hw_cal_data *caldata, bool fastcc);
924 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
925 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
926
927 /* GPIO / RFKILL / Antennae */
928 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
929 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
930 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
931 u32 ah_signal_type);
932 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
933 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
934
935 /* General Operation */
936 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
937 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
938 int column, unsigned int *writecnt);
939 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
940 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
941 u8 phy, int kbps,
942 u32 frameLen, u16 rateix, bool shortPreamble);
943 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
944 struct ath9k_channel *chan,
945 struct chan_centers *centers);
946 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
947 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
948 bool ath9k_hw_phy_disable(struct ath_hw *ah);
949 bool ath9k_hw_disable(struct ath_hw *ah);
950 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
951 void ath9k_hw_setopmode(struct ath_hw *ah);
952 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
953 void ath9k_hw_write_associd(struct ath_hw *ah);
954 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
955 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
956 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
957 void ath9k_hw_reset_tsf(struct ath_hw *ah);
958 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
959 void ath9k_hw_init_global_settings(struct ath_hw *ah);
960 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
961 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
962 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
963 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
964 const struct ath9k_beacon_state *bs);
965 bool ath9k_hw_check_alive(struct ath_hw *ah);
966
967 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
968
969 /* Generic hw timer primitives */
970 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
971 void (*trigger)(void *),
972 void (*overflow)(void *),
973 void *arg,
974 u8 timer_index);
975 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
976 struct ath_gen_timer *timer,
977 u32 timer_next,
978 u32 timer_period);
979 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
980
981 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
982 void ath_gen_timer_isr(struct ath_hw *hw);
983
984 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
985
986 /* PHY */
987 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
988 u32 *coef_mantissa, u32 *coef_exponent);
989 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
990 bool test);
991
992 /*
993 * Code Specific to AR5008, AR9001 or AR9002,
994 * we stuff these here to avoid callbacks for AR9003.
995 */
996 int ar9002_hw_rf_claim(struct ath_hw *ah);
997 void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
998
999 /*
1000 * Code specific to AR9003, we stuff these here to avoid callbacks
1001 * for older families
1002 */
1003 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
1004 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
1005 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
1006 void ar9003_hw_disable_phy_restart(struct ath_hw *ah);
1007 void ar9003_paprd_enable(struct ath_hw *ah, bool val);
1008 void ar9003_paprd_populate_single_table(struct ath_hw *ah,
1009 struct ath9k_hw_cal_data *caldata,
1010 int chain);
1011 int ar9003_paprd_create_curve(struct ath_hw *ah,
1012 struct ath9k_hw_cal_data *caldata, int chain);
1013 int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
1014 int ar9003_paprd_init_table(struct ath_hw *ah);
1015 bool ar9003_paprd_is_done(struct ath_hw *ah);
1016 void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains);
1017 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
1018
1019 /* Hardware family op attach helpers */
1020 void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
1021 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
1022 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
1023
1024 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
1025 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
1026
1027 void ar9002_hw_attach_ops(struct ath_hw *ah);
1028 void ar9003_hw_attach_ops(struct ath_hw *ah);
1029
1030 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
1031 /*
1032 * ANI work can be shared between all families but a next
1033 * generation implementation of ANI will be used only for AR9003 only
1034 * for now as the other families still need to be tested with the same
1035 * next generation ANI. Feel free to start testing it though for the
1036 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
1037 */
1038 extern int modparam_force_new_ani;
1039 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
1040 void ath9k_hw_proc_mib_event(struct ath_hw *ah);
1041 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
1042
1043 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
ath9k_hw_btcoex_is_enabled(struct ath_hw * ah)1044 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1045 {
1046 return ah->btcoex_hw.enabled;
1047 }
1048 void ath9k_hw_btcoex_enable(struct ath_hw *ah);
1049 static inline enum ath_btcoex_scheme
ath9k_hw_get_btcoex_scheme(struct ath_hw * ah)1050 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1051 {
1052 return ah->btcoex_hw.scheme;
1053 }
1054 #else
ath9k_hw_btcoex_is_enabled(struct ath_hw * ah)1055 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1056 {
1057 return false;
1058 }
ath9k_hw_btcoex_enable(struct ath_hw * ah)1059 static inline void ath9k_hw_btcoex_enable(struct ath_hw *ah)
1060 {
1061 }
1062 static inline enum ath_btcoex_scheme
ath9k_hw_get_btcoex_scheme(struct ath_hw * ah)1063 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1064 {
1065 return ATH_BTCOEX_CFG_NONE;
1066 }
1067 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
1068
1069 #define ATH9K_CLOCK_RATE_CCK 22
1070 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1071 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1072 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
1073
1074 #endif
1075