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/drivers/scsi/
Dnsp32.h92 # define IRQSTATUS_LATCHED_MSG BIT(0)
93 # define IRQSTATUS_LATCHED_IO BIT(1)
94 # define IRQSTATUS_LATCHED_CD BIT(2)
95 # define IRQSTATUS_LATCHED_BUS_FREE BIT(3)
96 # define IRQSTATUS_RESELECT_OCCUER BIT(4)
97 # define IRQSTATUS_PHASE_CHANGE_IRQ BIT(5)
98 # define IRQSTATUS_SCSIRESET_IRQ BIT(6)
99 # define IRQSTATUS_TIMER_IRQ BIT(7)
100 # define IRQSTATUS_FIFO_SHLD_IRQ BIT(8)
101 # define IRQSTATUS_PCI_IRQ BIT(9)
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/drivers/net/wireless/rtlwifi/rtl8192se/
Dreg.h327 #define RXDMA_AGG_EN BIT(7)
333 #define ISO_MD2PP BIT(0)
334 #define ISO_PA2PCIE BIT(3)
335 #define ISO_PLL2MD BIT(4)
336 #define ISO_PWC_DV2RP BIT(11)
337 #define ISO_PWC_RV2RP BIT(12)
340 #define FEN_MREGEN BIT(15)
341 #define FEN_DCORE BIT(11)
342 #define FEN_CPUEN BIT(10)
344 #define PAD_HWPD_IDN BIT(22)
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/drivers/net/wireless/rtlwifi/rtl8192de/
Dreg.h94 #define MAC0_ON BIT(7)
95 #define MAC1_ON BIT(0)
96 #define MAC0_READY BIT(0)
97 #define MAC1_READY BIT(0)
442 #define RATE_1M BIT(0)
443 #define RATE_2M BIT(1)
444 #define RATE_5_5M BIT(2)
445 #define RATE_11M BIT(3)
447 #define RATE_6M BIT(4)
448 #define RATE_9M BIT(5)
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Ddef.h153 #define CHIP_92D_SINGLEPHY BIT(9)
154 #define C_CUT_VERSION BIT(13)
155 #define D_CUT_VERSION ((BIT(12)|BIT(13)))
156 #define E_CUT_VERSION BIT(14)
169 #define CHIP_8723 BIT(0)
170 #define CHIP_92D BIT(1)
171 #define NORMAL_CHIP BIT(3)
172 #define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6)))
173 #define RF_TYPE_1T2R BIT(4)
174 #define RF_TYPE_2T2R BIT(5)
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/drivers/net/wireless/rtlwifi/rtl8192ce/
Dreg.h360 #define CMDEEPROM_EN BIT(5)
361 #define CMDEEPROM_SEL BIT(4)
362 #define CMD9346CR_9356SEL BIT(4)
367 #define GPIOSEL_ENBT BIT(5)
385 #define RRSR_1M BIT(0)
386 #define RRSR_2M BIT(1)
387 #define RRSR_5_5M BIT(2)
388 #define RRSR_11M BIT(3)
389 #define RRSR_6M BIT(4)
390 #define RRSR_9M BIT(5)
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/drivers/pinctrl/
Dpinctrl-sirf.c182 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
183 BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
184 BIT(17) | BIT(18),
187 .mask = BIT(31),
194 .funcmask = BIT(4),
204 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
205 BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
206 BIT(17) | BIT(18),
209 .mask = BIT(31),
212 .mask = BIT(16) | BIT(17),
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/drivers/staging/rtl8712/
Drtl8712_cmdctrl_bitdef.h28 #define _APSDOFF_STATUS BIT(15)
29 #define _APSDOFF BIT(14)
30 #define _BBRSTn BIT(13) /*Enable OFDM/CCK*/
31 #define _BB_GLB_RSTn BIT(12) /*Enable BB*/
32 #define _SCHEDULE_EN BIT(10) /*Enable MAC scheduler*/
33 #define _MACRXEN BIT(9)
34 #define _MACTXEN BIT(8)
35 #define _DDMA_EN BIT(7) /*FW off load function enable*/
36 #define _FW2HW_EN BIT(6) /*MAC every module reset */
37 #define _RXDMA_EN BIT(5)
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Drtl8712_fifoctrl_bitdef.h30 #define _TXSTATUS_OVF BIT(15)
33 #define _STATUSFF1_OVF BIT(7)
34 #define _STATUSFF1_EMPTY BIT(6)
35 #define _STATUSFF0_OVF BIT(5)
36 #define _STATUSFF0_EMPTY BIT(4)
37 #define _RXFF1_OVF BIT(3)
38 #define _RXFF1_EMPTY BIT(2)
39 #define _RXFF0_OVF BIT(1)
40 #define _RXFF0_EMPTY BIT(0)
58 #define _C2HFF_POLL BIT(4)
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Drtl8712_syscfg_bitdef.h36 #define iso_LDR2RP BIT(iso_LDR2RP_SHT) /* 1:isolation, 0:attach*/
40 #define FEN_DIO_SDIO BIT(FEN_DIO_SDIO_SHT)
42 #define FEN_SDIO BIT(FEN_SDIO_SHT)
44 #define FEN_USBA BIT(FEN_USBA_SHT)
46 #define FEN_UPLL BIT(FEN_UPLL_SHT)
48 #define FEN_USBD BIT(FEN_USBD_SHT)
50 #define FEN_DIO_PCIE BIT(FEN_DIO_PCIE_SHT)
52 #define FEN_PCIEA BIT(FEN_PCIEA_SHT)
54 #define FEN_PPLL BIT(FEN_PPLL_SHT)
56 #define FEN_PCIED BIT(FEN_PCIED_SHT)
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Dwifi.h32 #ifdef BIT
33 #undef BIT
35 #define BIT(x) (1 << (x)) macro
62 WIFI_CTRL_TYPE = (BIT(2)),
63 WIFI_DATA_TYPE = (BIT(3)),
64 WIFI_QOS_DATA_TYPE = (BIT(7)|BIT(3)), /*!< QoS Data */
70 WIFI_ASSOCRSP = (BIT(4) | WIFI_MGT_TYPE),
71 WIFI_REASSOCREQ = (BIT(5) | WIFI_MGT_TYPE),
72 WIFI_REASSOCRSP = (BIT(5) | BIT(4) | WIFI_MGT_TYPE),
73 WIFI_PROBEREQ = (BIT(6) | WIFI_MGT_TYPE),
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Drtl8712_interrupt_bitdef.h25 #define _CPUERR BIT(29)
26 #define _ATIMEND BIT(28)
27 #define _TXBCNOK BIT(27)
28 #define _TXBCNERR BIT(26)
29 #define _BCNDMAINT4 BIT(25)
30 #define _BCNDMAINT3 BIT(24)
31 #define _BCNDMAINT2 BIT(23)
32 #define _BCNDMAINT1 BIT(22)
33 #define _BCNDOK4 BIT(21)
34 #define _BCNDOK3 BIT(20)
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Drtl871x_debug.h44 #define _module_rtl871x_xmit_c_ BIT(0)
45 #define _module_xmit_osdep_c_ BIT(1)
46 #define _module_rtl871x_recv_c_ BIT(2)
47 #define _module_recv_osdep_c_ BIT(3)
48 #define _module_rtl871x_mlme_c_ BIT(4)
49 #define _module_mlme_osdep_c_ BIT(5)
50 #define _module_rtl871x_sta_mgt_c_ BIT(6)
51 #define _module_rtl871x_cmd_c_ BIT(7)
52 #define _module_cmd_osdep_c_ BIT(8)
53 #define _module_rtl871x_io_c_ BIT(9)
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/drivers/mmc/host/
Ddw_mmc.h69 #define SDMMC_CTRL_USE_IDMAC BIT(25)
70 #define SDMMC_CTRL_CEATA_INT_EN BIT(11)
71 #define SDMMC_CTRL_SEND_AS_CCSD BIT(10)
72 #define SDMMC_CTRL_SEND_CCSD BIT(9)
73 #define SDMMC_CTRL_ABRT_READ_DATA BIT(8)
74 #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7)
75 #define SDMMC_CTRL_READ_WAIT BIT(6)
76 #define SDMMC_CTRL_DMA_ENABLE BIT(5)
77 #define SDMMC_CTRL_INT_ENABLE BIT(4)
78 #define SDMMC_CTRL_DMA_RESET BIT(2)
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/drivers/net/wireless/ath/carl9170/
Dhw.h115 #define AR9170_MAC_INT_TXC BIT(0)
116 #define AR9170_MAC_INT_RXC BIT(1)
117 #define AR9170_MAC_INT_RETRY_FAIL BIT(2)
118 #define AR9170_MAC_INT_WAKEUP BIT(3)
119 #define AR9170_MAC_INT_ATIM BIT(4)
120 #define AR9170_MAC_INT_DTIM BIT(5)
121 #define AR9170_MAC_INT_CFG_BCN BIT(6)
122 #define AR9170_MAC_INT_ABORT BIT(7)
123 #define AR9170_MAC_INT_QOS BIT(8)
124 #define AR9170_MAC_INT_MIMO_PS BIT(9)
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/drivers/net/wireless/rtlwifi/
Ddebug.h79 #define COMP_ERR BIT(0)
80 #define COMP_FW BIT(1)
81 #define COMP_INIT BIT(2) /*For init/deinit */
82 #define COMP_RECV BIT(3) /*For Rx. */
83 #define COMP_SEND BIT(4) /*For Tx. */
84 #define COMP_MLME BIT(5) /*For MLME. */
85 #define COMP_SCAN BIT(6) /*For Scan. */
86 #define COMP_INTR BIT(7) /*For interrupt Related. */
87 #define COMP_LED BIT(8) /*For LED. */
88 #define COMP_SEC BIT(9) /*For sec. */
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/drivers/scsi/pcmcia/
Dnsp_cs.h40 # define IRQCONTROL_RESELECT_CLEAR BIT(0)
41 # define IRQCONTROL_PHASE_CHANGE_CLEAR BIT(1)
42 # define IRQCONTROL_TIMER_CLEAR BIT(2)
43 # define IRQCONTROL_FIFO_CLEAR BIT(3)
52 # define IRQSTATUS_SCSI BIT(0)
53 # define IRQSTATUS_TIMER BIT(2)
54 # define IRQSTATUS_FIFO BIT(3)
58 # define IF_IFSEL BIT(0)
59 # define IF_REGSEL BIT(2)
64 # define FIFOSTATUS_FULL_EMPTY BIT(7)
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/drivers/tty/serial/
Dsirfsoc_uart.h35 #define SIRFUART_DATA_BIT_LEN_5 BIT(0)
40 #define SIRFUART_STOP_BIT_LEN_2 BIT(2)
41 #define SIRFUART_PARITY_EN BIT(3)
42 #define SIRFUART_EVEN_BIT BIT(4)
45 #define SIRFUART_STICK_BIT_EVEN BIT(3)
49 #define SIRFUART_SET_BREAK BIT(6)
50 #define SIRFUART_LOOP_BACK BIT(7)
52 #define SIRFUART_DUMMY_READ BIT(16)
60 #define SIRFUART_AFC_RX_EN BIT(8)
61 #define SIRFUART_AFC_TX_EN BIT(9)
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/drivers/net/ethernet/sgi/
Dmeth.h117 #define SGI_MAC_RESET BIT(0) /* 0: MAC110 active in run mode, 1: Global reset signal to MAC110 cor…
118 #define METH_PHY_FDX BIT(1) /* 0: Disable full duplex, 1: Enable full duplex */
119 #define METH_PHY_LOOP BIT(2) /* 0: Normal operation, follows 10/100mbit and M10T/MII select, 1: loo…
121 #define METH_100MBIT BIT(3) /* 0: 10meg mode, 1: 100meg mode */
122 #define METH_PHY_MII BIT(4) /* 0: MII selected, 1: SIA selected */
132 #define METH_PHY_LINK_FAIL BIT(7) /* 0: Link failure detection disabled, 1: Hardware scans for link…
155 #define METH_DMA_TX_EN BIT(1) /* enable TX DMA */
156 #define METH_DMA_TX_INT_EN BIT(0) /* enable TX Buffer Empty interrupt */
157 #define METH_DMA_RX_EN BIT(15) /* Enable RX */
158 #define METH_DMA_RX_INT_EN BIT(9) /* Enable interrupt on RX packet */
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/drivers/net/wireless/wl1251/
Devent.h39 RESERVED1_EVENT_ID = BIT(0),
40 RESERVED2_EVENT_ID = BIT(1),
41 MEASUREMENT_START_EVENT_ID = BIT(2),
42 SCAN_COMPLETE_EVENT_ID = BIT(3),
43 CALIBRATION_COMPLETE_EVENT_ID = BIT(4),
44 ROAMING_TRIGGER_LOW_RSSI_EVENT_ID = BIT(5),
45 PS_REPORT_EVENT_ID = BIT(6),
46 SYNCHRONIZATION_TIMEOUT_EVENT_ID = BIT(7),
47 HEALTH_REPORT_EVENT_ID = BIT(8),
48 ACI_DETECTION_EVENT_ID = BIT(9),
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/drivers/net/wireless/wl12xx/
Devent.h41 RSSI_SNR_TRIGGER_0_EVENT_ID = BIT(0),
42 RSSI_SNR_TRIGGER_1_EVENT_ID = BIT(1),
43 RSSI_SNR_TRIGGER_2_EVENT_ID = BIT(2),
44 RSSI_SNR_TRIGGER_3_EVENT_ID = BIT(3),
45 RSSI_SNR_TRIGGER_4_EVENT_ID = BIT(4),
46 RSSI_SNR_TRIGGER_5_EVENT_ID = BIT(5),
47 RSSI_SNR_TRIGGER_6_EVENT_ID = BIT(6),
48 RSSI_SNR_TRIGGER_7_EVENT_ID = BIT(7),
49 MEASUREMENT_START_EVENT_ID = BIT(8),
50 MEASUREMENT_COMPLETE_EVENT_ID = BIT(9),
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/drivers/input/mouse/
Dsentelic.h30 #define FSP_BIT_NO_ROTATION BIT(3)
35 #define FSP_BIT_EN_REG_CLK BIT(5)
38 #define FSP_BIT_EN_OPC_TAG BIT(7)
44 #define FSP_BIT_90_DEGREE BIT(0)
45 #define FSP_BIT_EN_MSID6 BIT(1)
46 #define FSP_BIT_EN_MSID7 BIT(2)
47 #define FSP_BIT_EN_MSID8 BIT(3)
48 #define FSP_BIT_EN_AUTO_MSID8 BIT(5)
49 #define FSP_BIT_EN_PKT_G0 BIT(6)
52 #define FSP_BIT_ONPAD_ENABLE BIT(0)
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/drivers/net/ethernet/smsc/
Dsmsc9420.h55 #define BUS_MODE_SWR_ (BIT(0))
56 #define BUS_MODE_DMA_BURST_LENGTH_1 (BIT(8))
57 #define BUS_MODE_DMA_BURST_LENGTH_2 (BIT(9))
58 #define BUS_MODE_DMA_BURST_LENGTH_4 (BIT(10))
59 #define BUS_MODE_DMA_BURST_LENGTH_8 (BIT(11))
60 #define BUS_MODE_DMA_BURST_LENGTH_16 (BIT(12))
61 #define BUS_MODE_DMA_BURST_LENGTH_32 (BIT(13))
62 #define BUS_MODE_DBO_ (BIT(20))
75 #define DMAC_STS_NIS_ (BIT(16))
76 #define DMAC_STS_AIS_ (BIT(15))
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/drivers/usb/gadget/
Dci13xxx_udc.h35 #define TD_TERMINATE BIT(0)
40 #define TD_STATUS_TR_ERR BIT(3)
41 #define TD_STATUS_DT_ERR BIT(5)
42 #define TD_STATUS_HALTED BIT(6)
43 #define TD_STATUS_ACTIVE BIT(7)
45 #define TD_IOC BIT(15)
58 #define QH_IOS BIT(15)
60 #define QH_ZLT BIT(29)
107 #define CI13XXX_REGS_SHARED BIT(0)
108 #define CI13XXX_REQUIRE_TRANSCEIVER BIT(1)
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/drivers/edac/
Damd8111_edac.h32 PCI_STSCMD_SSE = BIT(30),
33 PCI_STSCMD_RMA = BIT(29),
34 PCI_STSCMD_RTA = BIT(28),
35 PCI_STSCMD_SERREN = BIT(8),
46 MEM_LIMIT_DPE = BIT(31),
47 MEM_LIMIT_RSE = BIT(30),
48 MEM_LIMIT_RMA = BIT(29),
49 MEM_LIMIT_RTA = BIT(28),
50 MEM_LIMIT_STA = BIT(27),
51 MEM_LIMIT_MDPE = BIT(24),
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/drivers/mfd/
Ddbx500-prcmu-regs.h18 #define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end))
77 #define PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN BIT(0)
78 #define PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN BIT(1)
116 #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE BIT(0)
117 #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE BIT(1)
118 #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_VMODEM_OFF_ISO BIT(2)
136 #define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP BIT(11)
137 #define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI BIT(22)
149 #define PRCM_PLL_FREQ_SELDIV2 BIT(24)
150 #define PRCM_PLL_FREQ_DIV2EN BIT(25)
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