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Searched refs:BIT4 (Results 1 – 25 of 31) sorted by relevance

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/drivers/scsi/
Dtmscsim.h187 #define BIT4 0x00000010 macro
210 #define SRB_MSGIN_MULTI BIT4
227 #define PARITY_ERROR BIT4
242 #define ENABLE_TIMER BIT4
282 #define EN_TAG_QUEUEING BIT4
337 #define TAG_QUEUEING_ BIT4
344 #define NO_SEEK BIT4
392 #define COUNT_2_ZERO BIT4
401 #define SERVICE_REQUEST BIT4
424 #define PARITY_ERR_REPO BIT4
[all …]
Ddc395x.h71 #define BIT4 0x00000010 macro
132 #define PARITY_ERROR BIT4
139 #define ENABLE_TIMER BIT4
177 #define WIDE_NEGO_STATE BIT4
633 #define NO_SEEK BIT4
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h115 #define EPROM_CMD_9356SEL BIT4
219 #define SCR_SKByA2 BIT4
238 #define IMR_BKDOK BIT4
249 #define TPPoll_BQ BIT4
289 #define AcmHw_BeqStatus BIT4
379 #define RRSR_6M BIT4
Drtl_pci.c45 tmp |= BIT4; in rtl8192_parse_pci_configuration()
/drivers/staging/vt6655/
D80211hdr.h42 #define BIT4 0x00000010 macro
166 #define WLAN_GET_FC_FSTYPE(n) ((((unsigned short)(n) >> 8) & (BIT4|BIT5|BIT6|BIT7)) >> 4)
186 #define WLAN_GET_CAP_INFO_PRIVACY(n) ((((n) >> 8) & BIT4) >> 4)
201 #define WLAN_GET_FC_FSTYPE(n) ((((unsigned short)(n)) & (BIT4|BIT5|BIT6|BIT7)) >> 4)
222 #define WLAN_GET_CAP_INFO_PRIVACY(n) (((n) & BIT4) >> 4)
Dhostap.h40 #define WLAN_RATE_6M BIT4
Dbssdb.h60 #define WLAN_STA_PERM BIT4
/drivers/staging/vt6656/
D80211hdr.h40 #define BIT4 0x00000010 macro
163 & (BIT4|BIT5|BIT6|BIT7)) >> 4)
183 #define WLAN_GET_CAP_INFO_PRIVACY(n) ((((n) >> 8) & BIT4) >> 4)
197 #define WLAN_GET_FC_FSTYPE(n) ((((WORD)(n)) & (BIT4|BIT5|BIT6|BIT7)) >> 4)
216 #define WLAN_GET_CAP_INFO_PRIVACY(n) (((n) & BIT4) >> 4)
Dhostap.h40 #define WLAN_RATE_6M BIT4
Dbssdb.h61 #define WLAN_STA_PERM BIT4
/drivers/staging/rtl8192u/
Dr8192U_hw.h187 #define SCR_SKByA2 BIT4 //Search kEY BY A2
233 #define AcmHw_BeqStatus BIT4
311 #define RRSR_6M BIT4
Dr8192U.h55 #define BIT4 0x00000010 macro
102 #define COMP_SEND BIT4 // Send part path.
Dr819xU_phy.c1082 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4] in rtl8192_SetRFPowerState()
1103 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); // 0x860[4] in rtl8192_SetRFPowerState()
/drivers/video/via/
Ddvi.c75 viafb_write_reg_mask(SR1E, VIASR, 0xF0, BIT4 + in viafb_tmds_trasmitter_identify()
340 viafb_write_reg_mask(SR2A, VIASR, 0, BIT4); in dvi_patch_skew_dvp0()
361 viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4); in dvi_patch_skew_dvp0()
Dhw.c962 viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4); in load_fix_bit_crtc_reg()
1728 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1732 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5); in set_display_channel()
1735 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5); in set_display_channel()
1740 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1743 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5); in set_display_channel()
2076 BIT4); in viafb_set_dpa_gfx()
Dshare.h32 #define BIT4 0x10 macro
Dlcd.c857 bdual = BIT4; in fill_lcd_format()
861 viafb_write_reg_mask(CR88, VIACR, (bdithering | bdual), BIT4 + BIT0); in fill_lcd_format()
/drivers/staging/keucr/
Dsmilecc.c44 #define BIT4 0x10 macro
/drivers/tty/
Dsynclink.c493 #define RECEIVE_DATA BIT4
510 #define RXSTATUS_RXBOUND BIT4
549 #define TXSTATUS_EOF_SENT BIT4
550 #define TXSTATUS_EOM_SENT BIT4
570 #define MISCSTATUS_CTS BIT4
595 #define SICR_CTS_INACTIVE BIT4
596 #define SICR_CTS (BIT5+BIT4)
630 #define TXSTATUS_EOF BIT4
4728 RegValue |= BIT4; in usc_set_sdlc_mode()
5000 RegValue |= BIT4; /* enable BRG1 */ in usc_set_sdlc_mode()
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Dsynclinkmp.c424 #define SYNCD BIT4
425 #define FLGD BIT4
440 #define FRME BIT4
441 #define RBIT BIT4
2606 if (timerstatus0 & (BIT5 | BIT4)) in synclinkmp_interrupt()
2610 if (timerstatus1 & (BIT5 | BIT4)) in synclinkmp_interrupt()
4410 case 7: RegValue |= BIT4 + BIT2; break; in async_mode()
4412 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break; in async_mode()
4543 RegValue |= BIT4; in hdlc_mode()
4545 RegValue |= BIT4; in hdlc_mode()
[all …]
Dsynclink_gt.c386 #define MASK_OVERRUN BIT4
424 #define IRQ_RI BIT4
2239 if (status & (BIT5 + BIT4)) { in isr_rdma()
2264 if (status & (BIT5 + BIT4 + BIT3)) { in isr_tdma()
4161 case 6: val |= BIT4; break; in async_mode()
4163 case 8: val |= BIT5 + BIT4; break; in async_mode()
4201 case 6: val |= BIT4; break; in async_mode()
4203 case 8: val |= BIT5 + BIT4; break; in async_mode()
4327 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break; in sync_mode()
4328 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break; in sync_mode()
[all …]
/drivers/staging/rtl8187se/
Dr8180_hw.h28 #define BIT4 0x00000010 macro
/drivers/char/pcmcia/
Dsynclink_cs.c673 #define CMD_START_TIMER BIT4
3009 val = read_reg(info, CHA + CCR2) | (BIT4 + BIT5); in loopback_enable()
3096 val |= BIT4; in hdlc_mode()
3099 val |= BIT4 + BIT2; in hdlc_mode()
3102 val |= BIT4 + BIT3; in hdlc_mode()
3138 val |= BIT4; in hdlc_mode()
3505 val |= BIT4; in async_mode()
3662 if (!(status & BIT7) || (status & BIT4)) in rx_get_frame()
/drivers/staging/rtl8192e/
Drtl819x_Qos.h28 #define BIT4 0x00000010 macro
/drivers/staging/rtl8192u/ieee80211/
Drtl819x_Qos.h8 #define BIT4 0x00000010 macro

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